Device with host indication combination

Details Device with host indication combination Device with host indication combination

1992-09-18

1994-06-07

Shaw, Dale M.

395200, G06F 1314

Patent

active

053197526

ABSTRACT:
Combined indication signals of data block transfers are generated by a device which reduces the number of interrupts to a host processor. The reduction in the number of interrupts enhances host system performance during data block transfers. An embodiment of the device may be a network adapter comprising network interface logic for transferring a data frame between a network and a buffer memory and host interface logic for transferring a data frame between a buffer memory and a host system. The network adapter further includes threshold logic for generating an early receive indication signal when a portion of the data frame is received. Indication combination logic delays the generation of a transfer complete interrupt to slightly before the expected occurrence of the early receive indication. The host processor is able to service both the transfer complete indication and the early receive indication in a single interrupt service routine caused by the transfer complete indication.

REFERENCES:
patent: 4546467 (1985-10-01), Yamamoto
patent: 4680581 (1987-07-01), Kospik et al.
patent: 4866666 (1989-09-01), Francisco
patent: 5101402 (1992-03-01), Chiu et al.
patent: 5103446 (1992-04-01), Fischer

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