Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
1999-03-26
2001-06-26
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185330, C365S185010, C365S185050
Reexamination Certificate
active
06252799
ABSTRACT:
BACKGROUND
This invention relates generally to devices including embedded nonvolatile memories.
Nonvolatile memory cells are advantageous since they retain recorded information even when the power to the memory is turned off. There are several different types of non-volatile memories including erasable progammable read only memories (EPROMs), electrically eraseable and programmable read only memories (EEPROMs) flash EEPROM memories. EPROMs are erasable through light exposure but are electrically programmable by channel hot electron injection onto a floating gate. Conventional EEPROMs have the same programming functionality, but instead being light erasable they can be erased and programmed by electron tunneling. Thus, information may be stored in these memories, retained when the power is off, and the memories may be erased for reprogramming, as necessary, using appropriate techniques. Flash EEPROMs may be block erased, typically giving them better read access times than regular EEPROMs.
Currently, flash memories have gained considerable popularity. For example, flash memories are often utilized to provide on-chip memory for microcontrollers, modems and SMART cards and the like where it is desirable to store codes that may need fast updating.
While flash memories and EEPROMs are closely related, in many instances flash memories are preferred because their smaller cell size means that they can be made more economically. However, flash memories and EEPROMs often have very similar cell attributes.
Nonvolatile memory cells differ in certain respects from the transistors that are generally utilized in electronic components called logic devices, such as microcontrollers, that work with the memory cells. Logic devices are formed of transistors that use a single gate electrode. Nonvolatile memories usually include two gate electrodes, known as the control and floating gate electrodes, situated one over the other. Because of this structural difference, nonvolatile memories and logic devices may be made by different processes. This may contribute to a substantial increase in process complexity and manufacturing cost.
Particularly with an EEPROM, the electrical programming of the cells normally requires substantial potentials to be applied to the cells. These potentials induce electron tunneling from an N+ region onto the floating gate. Additional complexity may arise from the need to provide substantially larger voltages to memory cells than are needed for normal transistor operation.
While the industry has come to accept the need for separate process technologies for logic and nonvolatile memories and while those in the industry have also come to appreciate that significant currents to program flash EEPROMs, there would be a substantial demand for a nonvolatile memory which was both electrically erasable and programmable without the need for special process technologies or for relatively higher programming voltages and higher currents.
Furthermore, with the conventional FLASH EEPROMs, the electrical programming of the cells normally requires high current to be applied to the cells. A very minute amount of this electron current becomes injected from the drain depletion region onto the floating gate. This means that the injection efficiency of such devices is low (e.g., 1×10
−9
). The requirement of high current adds additional complexity because of the design of the high current pump operated at low voltage.
Conventionally, three approaches have been utilized to integrating FLASH and EEPROM onto a single integrated circuit die. One technique is to build both the EEPROM and FLASH devices using an appropriate process technologies to create the two different types of devices on the same die. However, this results in a dramatic increase in the number of process steps involved and therefore greatly increases the cost of the resulting device. Therefore, such techniques have not met with considerable acceptance in the industry.
Alternatively, a basic FLASH memory may be created and an additional FLASH portion may be adapted to emulate EEPROM memory. This normally involves building software into the FLASH memory so that the FLASH appears to operate as EEPROM memory. The software is stored in a boot block which is also a FLASH memory. Thus, the system needs a first FLASH memory to act as FLASH, a second FLASH memory to store the software needed to emulate EEPROM operation and additional FLASH memory to actually implement the FLASH-like capabilities. This results in a very costly structure whose operation is complicated. Thus, this technique has also not met with consideration administrative acceptance.
The third technique is to use an EEPROM memory to emulate a FLASH memory. However, EEPROM memories are generally large and therefore tend to be much more expensive. In fact, EEPROM memories may be three to four times larger than FLASH memories. Therefore, this approach is generally not considered to be commercially viable and has similarly failed to meet with considerable commercial acceptance.
Thus, there is a continuing need to find ways to build both EEPROM and FLASH capabilities into a single integrated circuit die. circuits, a second portion including an EEPROM memory and a third portion including a FLASH memory.
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Liu David K.
Wong Ting-wah
Nguyen Viet Q.
Programmable Silicon Solutions
Trop Pruner & Hu P.C.
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