Device under test de-embedding

Data processing: measuring – calibrating – or testing – Measurement system – Performance or efficiency evaluation

Reexamination Certificate

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Details

C324S638000, C702S117000, C702S126000, C703S013000, C703S014000, C714S733000, C714S734000

Reexamination Certificate

active

07920987

ABSTRACT:
A method of determining the intrinsic electrical characteristics of a device under test (DUT) includes determining a set of test measurements for a test structure including the device and determining test measurements for a number of de-embedding test structures. Based on the test measurements, DUT measurements are determined using both open-short and three-step de-embedding processes. The DUT measurements are combined to determine an imperfection error, which is used to adjust the calculations of a four-port de-embedding method. The adjusted calculations provide for a more accurate measurement of the parasitic elements in the test structure, thereby improving the determination of the intrinsic electrical characteristics of the device.

REFERENCES:
patent: 4680538 (1987-07-01), Dalman et al.
patent: 4680761 (1987-07-01), Burkness
patent: 6961669 (2005-11-01), Brunsman
Cho, et al., “A Three-Step Method for the De-Embedding of High-Frequency S-Parameter Measurements,” IEEE Transactions on Electron Devices, vol. 38, No. 6, Jun. 1991, pp. 1371-1375.
Koolen, et al., “An Improved De-Embedding Technique for On-Wafer High-Frequency Characterization,” IEEE 1991 Bipolar Circuits and Technology Meeting, 8.1, pp. 188-191.
Liang, et al., “A Simple Four-Point Parasitic Deembedding Methodology for High-Frequency Scattering Parameter and Noise Characterization of SiGe HBTs,” IEEE Transactions of Microwave Theory and Techniques, vol. 51, No. 11, Nov. 2003, pp. 2165-2174.
Vandamme, et al., “Improved Three-Step De-Embedding Method to Accurately Account for the Influence of Pad Parasitics in Silicon On-Wafer RF Test-Structures,” IEEE Transactions on Electron Devices, vol. 48, No. 4, Apr. 2001, pp. 737-742.

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