Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-09-23
2004-06-08
Karlsen, Ernest (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB
Reexamination Certificate
active
06747473
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an integrated circuit testing device generally and, more particularly, to a device under test (DUT) interface card with on-board testing.
BACKGROUND OF THE INVENTION
Conventional integrated circuit (IC) wafer testing involves interconnecting extremely expensive diagnostic tools with each die on a wafer. Automatic Test Equipment (ATE) tester, ATE interface assemblies, and interface cards are the main components used to test integrated circuit wafers. In conventional approaches, the automatic test equipment is connected to a DUT card using ATE interface assemblies. The DUT card forms connections with the wafer or packaged integrated circuit. The automatic test equipment generates the electronic test sequence and applies the test sequence to the DUT card using cable interfacing and the interface assemblies.
Referring to
FIG. 1
, a block diagram is shown illustrating a conventional automatic test equipment probe card application. An automatic test equipment
12
is connected to a probe card
14
that performs tests on a wafer
16
. In an analysis environment, the ATE
12
is connected to the probe card
14
with high quality, expensive cable interfacing
18
. The cable interfacing
18
is often long. The automatic test equipment
12
generates an electronic test sequence and applies the test sequence to the probe card
14
via the cable interfacing
18
. The probe card
14
then applies the test sequence to the wafer
16
using the local interface path
20
. Typically, no logic exists on the probe card
14
. The ATE
12
is responsible for controlling the test procedure, generating the test sequence, and receiving the test results.
Problems with conventional approaches include that high speed, high pin count testers with scan capability are expensive and typically not available in the failure analysis lab. Also, the cable interfacing
18
between the probe card
14
and the tester
12
is expensive and cumbersome. Conventional solutions to this problem implement Built-In Self-Test (BIST) circuitry on the dies being fabricated to avoid having to perform high speed automatic tests of the wafers after production using complicated test equipment. However, built-in self-test methodology does not (i) fully test the device to prove that the device is good and/or (ii) adequately condition the device for failure analysis techniques.
It would be desirable to have an interface card that generates test signals locally so that expensive, high-tech interfaces between the automatic test equipment and the probe card are not needed and/or the automatic test equipment would not be needed to perform the test, particularly when the device is connected to analysis equipment.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first plurality of contacts, a second plurality of contacts, one or more sockets, and a programmable processor. The first plurality of contacts may be configured to receive one or more first signals. The second plurality of contacts may be configured to present one or more second signals in response to the one or more first signals. The one or more sockets may be configured to receive one or more third signals from one or more programmable devices. The programmable processor may be configured to generate a test signal in response to (i) the one or more first signals and (ii) the one or more third signals.
The objects, features and advantages of the present invention include providing a device under test interface card with on-board test that may (i) be implemented without high speed, high pin count testers with scan capability in the failure analysis lab, (ii) be implemented without expensive, bulky cabling, (iii) be easily manipulated in various failure analysis equipment setups that have tight interface constraints, (iv) allow at-speed, real-time testing (or configuring) due to the capability of replacing the long signal delay paths from the tester through the cable interface to the device under test with short delay paths between the on-board processors and/or memories of the interface card and the device under test, (v) provide multiple setups to operate independently after being programmed by a single programmer, (vi) be implemented without the automatic test equipment to execute tests on the device under test, and/or (vii) allow simple testers to be connected to the probe card.
REFERENCES:
patent: 4780670 (1988-10-01), Cherry
patent: 5070297 (1991-12-01), Kwon et al.
Karlsen Ernest
LSI Logic Corporation
Maiorana PC Christopher P.
Nguyen Tung X.
LandOfFree
Device under interface card with on-board testing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Device under interface card with on-board testing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device under interface card with on-board testing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3301717