Device, system and method of delay calibration

Details Device, system and method of delay calibration Device, system and method of delay calibration

2007-10-07

2009-10-20

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S161000, C327S271000, C327S277000

Reexamination Certificate

active

07605625

ABSTRACT:
System and method of calibrating delay mismatch for high-spectral purity applications. For example, a method includes measuring the delay of one delay element at a time in a fixed topology by moving a time reference generated by an auxiliary delay-locked loop. The auxiliary DLL may have a replica structure of the primary DLL being calibrated. The calibration method uses one output clock signal of the primary DLL and measures delay mismatch using a reference phase previously measured using the same topology. The calibration method takes into account all delay mismatches in the topology up to the primary DLL output clock signal, including any delay generated by an associated multiplexer.

REFERENCES:
patent: 6194928 (2001-02-01), Heyne
patent: 7154978 (2006-12-01), Juan et al.
patent: 7355380 (2008-04-01), Abuhamdeh et al.
patent: 7439787 (2008-10-01), Hashim et al.
Chan-Hong Park, Ook Kim, and Beomsup Kim, “A 1.8-GHz Self-Calibrated Phase-Locked Loop with Precise I/Q Matching,” in IEEE Journal of Solid-State Circuits, vol. 36, Issue 5, May 2001, pp. 777-783.

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