Device jointly implementing a post-processing and a decoding...

Details Device jointly implementing a post-processing and a decoding... Device jointly implementing a post-processing and a decoding...

2005-06-21

2005-06-21

Philippe, Gims (Department: 2613)

Pulse or digital communications

Bandwidth reduction or expansion

Television or motion video signal

C382S233000, C348S419100

Reexamination Certificate

active

06909751

ABSTRACT:
The present invention relates to a device for processing blocks of coded data included in a sequence of coded digital images (ES) according to a block-based coding technique, said device comprising a post-processing circuit DFD (33). Such a device effectively corrects the blocking artifacts while minimizing the bandwidth used, the decoder directly transmitting decoded data blocks (B) to the post-processing circuit. In addition, such a device introduces no or little drift during the decoding since the decoder continues to use reference images (RB) during a motion compensation step. This is because the reference images are no longer the decoded images but the completely processed images as the post-processing circuit is situated in the decoding loop.

REFERENCES:
patent: 5991494 (1999-11-01), Otsuka
patent: 6259741 (2001-07-01), Chen et al.
patent: 6477679 (2002-11-01), Such et al.
patent: 6732328 (2004-05-01), McEwen et al.
“A Projection-Based Post-Processing Technique to Reduce Blocking Artifacts Using a Priori Information on DCT Coeffeicients of Adjacent Blocks” published by Hoon Paek and Sang-Uk Lee in Proceedings of 3rdIEEE International Conference on Image Processing, vol. 32, Lausanne, Switzerland, Sept. 16-19, 1996, pp 53-56.

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