Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-01-20
2001-01-09
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S446000, C438S501000
Reexamination Certificate
active
06171930
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a device isolation structure and a device isolation method in a semiconductor power integrated circuit (IC) capable of isolating a common region between a high voltage device region and a low voltage device region using a field insulating film according to a local oxidation of silicon (LOCOS), applying a silicon on insulator (SOI).
2. Discussion of the Background
As semiconductor devices have become highly integrated and fabricating techniques thereof have been developed, attempts to achieve a single-chip system have been made. According to the single-chip system, a single chip is constructed with a controller, a memory, and a circuit operated at a low voltage. In order to achieve the single-chip system that is light in weight and compact in size, the system should integrate a circuit unit controlling a power source of the system, which includes an input terminal, an output terminal, and a main circuit as a single chip. Each of the input and output terminals, to which a high voltage (HV) is applied, is constructed as a HV power transistor since a low voltage (LV) CMOS circuit can not be applied thereto.
Accordingly, to reduce its weight and size, the input and output terminals of the power source and the controller must be integrated as a single chip. To accomplish the above object, IC techniques have been developed for constructing the HV transistor (hereinafter, called HV TR) and the LV CMOS circuit as a single chip.
According to the prior art, a wafer having a thick epi-layer having a deep junction depth is used to achieve HV breakdown. However, a process of forming a wafer having such a deep junction depth requires a lengthy diffusion time on the order of thousands of minutes. In addition, a device between a HV TR and another TR must be isolated by a junction isolation or a self-isolation method, thus lowering throughput and enlarging chip size. Further, it is difficult to integrate the process of forming the deep junction depth with a general CMOS process. Therefore, a power IC technique involving the application of a SOI substrate has been introduced to overcome the disadvantages of the IC technique.
According to the SOI power IC technique, the deep junction depth is not required. In addition, a chip size can be reduced by isolating devices according to a trench isolation method in the SOI power IC technique to improve the throughput of the resulting structure. Above all, the SOI power IC technique can easily be integrated with the general CMOS technique.
In the power IC technique using the SOI substrate, a HV device region is isolated by the trench method, and a LV CMOS region is isolated by a LOCOS method. The main processes involved in the power IC technique are a device isolation method for continuously connecting the two regions and a method for forming a field.
According to the conventional method, the HV device region is isolated by a trench, the LV CMOS region is isolated by a LOCOS, and an interfacing region therebetween is embodied as a field oxide film applying a CVD oxide film (SiO
2
).
Hereinafter, a device isolation structure and a device isolation method in the conventional semiconductor power IC will be described with reference to the accompanying drawings.
FIG. 1
is a vertical cross-sectional diagram of a device isolation structure of the conventional semiconductor power IC. As shown therein, the conventional device isolation structure includes: a semiconductor SOI substrate
1
which includes a HV device region
1
hr in which a HV TR is to be formed, and a LV device region
1
lr in which a LV CMOS circuit is to be formed; a trench
4
overlapping the HV device region
1
hr and an interfacing region
1
ir that is positioned between the HV device region
1
hr and the LV device region
1
lr; a polysilicon film
6
filled in the trench
4
; a second SiO
2
film
7
formed on a resultant upper surface of the semiconductor SOI substrate
1
; a third high temperature low pressure deposition (HLD) SiO
2
film
8
formed on a predetermined portion of an upper surface of the second SiO
2
film
7
corresponding to the trench
4
; and a field insulating film
7
a
formed on a portion of the semiconductor SOI substrate
1
, which field insulating film
7
a
extends from a surface of SOI substrate
1
through second SiO
2
film
7
.
A second HLD SiO
2
film
5
is formed between the trench
4
and the polysilicon film
6
, and the field insulating film
7
a
is formed at the interfacing region
1
ir and the LV device region
1
lr, respectively, and the field insulating film
7
a
at the interfacing region
1
ir is adjacent to the third HLD SiO
2
film
8
.
FIGS. 2A-2P
sequentially illustrate a device isolation method of the conventional semiconductor power IC.
In
FIG. 2A
, a first HLD SiO
2
film
2
for a hard mask is formed at a thickness of 1000 A on a semiconductor SOI substrate
1
by high temperature low pressure deposition (HLD). Hereinafter, a silicon oxide film formed by HLD is called a HLD SiO
2
film. The SOI substrate
1
is divided into two parts, a HV device region
1
hr in which a HV TR is to be formed and a LV device region
1
lr in which a LV CMOS is to be formed. An interfacing region may be defined between the HV device region
1
hr and the LV device region
1
lr in the final step. A general photoresist film is not applied for the hard mask since it has low selectivity with respect to Si etching, rendering it incapable of serving as the mask.
In
FIG. 2B
, a first photoresist pattern
3
is formed on the first HLD SiO
2
film
2
, and a predetermined portion of the first HLD SiO
2
film
2
is etched by using the first photoresist pattern
3
as a mask. A portion of an upper surface of the SOI substrate
1
corresponding to the etched portion of the first HLD SiO
2
film
2
is exposed in this etching process.
In
FIG. 2C
, the first photoresist pattern
3
is removed, and a trench
4
is formed by which the exposed portion of a silicon layer
1
a
of the SOI substrate
1
is etched using the remaining portion of first HLD SiO
2
film
2
as the hard mask. In this etching process, an insulating layer
1
b
of the SOI substrate
1
is exposed.
In
FIG. 2D
, a thin first SiO
2
film (not shown) is applied on the first HLD SiO
2
film
2
including the trench
4
by a thermal oxidation method, and a second HLD SiO
2
film
5
at a thickness of 1400 A is formed in a conformal manner on a resultant upper surface of the SOI substrate
1
including the trench
4
. The first SiO
2
film (not shown) is formed at 900° C. under an oxygen/hydrogen atmosphere.
In
FIG. 2E
, enough polysilicon film
6
is deposited on the second HLD SiO
2
film
5
formed on the SOI substrate
1
, including the trench
4
, to completely fill up the trench
4
. The thicknesses of the second HLD SiO
2
film
5
and the polysilicon film
6
are determined in accordance with width of the trench
4
, so that the trench
4
can be completely filled.
In
FIG. 2F
, an etch back process is applied to the polysilicon film
6
in order to expose a portion of an upper surface of the second HLD SiO
2
film
5
formed on the SOI substrate
1
, excluding a portion thereof corresponding to the trench
4
.
In
FIG. 2G
, in order to expose a portion of the upper surface of the SOI substrate
1
, excluding the part corresponding to the trench
4
, the first HLD SiO
2
film
2
and the second HLD SiO
2
film
5
are removed by a HF etching solution. A portion of the second HLD SiO
2
film
5
that is formed between the trench
4
and the polysilicon film
6
remains after this etching process is performed.
In
FIG. 2H
, a second SiO
2
film
7
having a thickness of 400 A is formed on the SOI substrate
1
and the trench
4
by the thermal oxidation method, and a thin third HLD SiO
2
film
8
is formed on the second SiO
2
film
7
. The third HLD SiO
2
film
8
is thinly formed, so that breakdown may not be generated in an interconnection of the HV d
Ju Jae-Il
Lee Chang-Jae
Hyundai Electronics Industries Co,. Ltd.
Niebling John F.
Pompey Ron
LandOfFree
Device isolation structure and device isolation method for a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Device isolation structure and device isolation method for a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device isolation structure and device isolation method for a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2503342