Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
1998-05-14
2001-01-16
Hardy, David (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S640000, C257S410000
Reexamination Certificate
active
06175147
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor fabrication processing and more particularly to a method for forming isolation for Complimentary Metal Oxide Semiconductor (CMOS) devices.
BACKGROUND OF THE INVENTION
The continuing trend of scaling down integrated circuits has forced the semiconductor industry to consider new techniques for fabricating smaller components at sub-micron levels. With the industry moving towards processes for fabrication of smaller device geometries, isolation between devices becomes a very critical issue.
Several isolation methods are currently prevalent in the semiconductor industry. One method, LOCal Oxidation of Silicon (LOCOS) uses patterned silicon nitride as an oxidation inhibitor so that the silicon substrate will oxidize where the nitride is removed and not oxidize where the nitride is present. A main fabrication concern when using LOCOS is the encroachment of oxide under the nitride that causes the well known “bird's-beak” problem.
A second isolation method is deep trench isolation, where a single deep trench is etched into the silicon substrate and then filled with oxide. However, deep trenches have proven difficult to reliably manufacture over an entire wafer and the width of the trench is limited to the critical dimension of a given process.
The present invention develops a method to fabricate device isolation for sub-micron fabrication processes. In particular, the present invention provides a device isolation method for processes using a device geometry of 0.18 &mgr;m or smaller.
SUMMARY OF THE INVENTION
An exemplary implementation of the present invention discloses an isolation structure and processes for fabricating the isolation structure for a semiconductor device.
In a general aspect of the present invention, a semiconductor assembly having at least one isolation structure is formed. The semiconductor assembly may simply comprise a trench in a semiconductive substrate, the trench being filled with an insulation material. In a preferred general embodiment, the semiconductor assembly comprises: a first trench in a semiconductive substrate; a second trench extending the overall trench depth in the semiconductive substrate by being aligned to the first trench; and an insulation material substantially filling the first and second trenches. The isolation structure separates a noncontinuous surface of a conductive region.
General process steps to form the isolation structure comprise: forming a mask over a semiconductor substrate assembly; forming a first trench into the semiconductor substrate assembly using the mask as an etching guide; forming an insulation layer on the surface of the first trench, forming a semiconductive spacer on the side wall of the first trench; forming a second trench into the semiconductor substrate assembly at the bottom of the first trench by using the semiconductive spacer as an etching guide; forming an isolation filler in the first and second trenches, the isolation filler substantially consuming the semiconductive spacer and thereby substantially filling the first and second trenches; and planarizing the isolation filler. If sufficient for a given process, the steps to form a second trench could be skipped and the isolation filler would then be formed in a first trench.
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Hardy David
Micro)n Technology, Inc.
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