Device having programmable resources and a method of...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing

Reexamination Certificate

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Reexamination Certificate

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07979827

ABSTRACT:
A method of configuring a device having programmable logic is disclosed. The method comprises generating a netlist associated with a circuit design; coupling the netlist to the device having programmable logic; performing a re-targeting function using a circuit on the device having programmable logic; generating configuration bits for configuring the programmable logic; and configuring the programmable logic to implement the circuit design according to the configuration bits based upon the netlist and results of the re-targeting function.

REFERENCES:
patent: 5748979 (1998-05-01), Trimberger
patent: 5815405 (1998-09-01), Baxter
patent: 5968161 (1999-10-01), Southgate
patent: 6078735 (2000-06-01), Baxter
patent: 6078736 (2000-06-01), Guccione
patent: 6311316 (2001-10-01), Huggins et al.
patent: 6625787 (2003-09-01), Baxter et al.
patent: 6725441 (2004-04-01), Keller et al.
patent: 6894527 (2005-05-01), Donlin et al.
patent: 6938236 (2005-08-01), Park et al.
patent: 7111224 (2006-09-01), Trimberger
patent: 7207020 (2007-04-01), Fung et al.
patent: 7251804 (2007-07-01), Trimberger
patent: 7284229 (2007-10-01), Trimberger
patent: 7310794 (2007-12-01), Squires
patent: 7315972 (2008-01-01), Bapat
patent: 7417918 (2008-08-01), Hao et al.
patent: 7610573 (2009-10-01), Chan et al.
Goldstein, Seth Copen et al., “PipeRench: A Reconfigurable Architecture and Compiler,”Computer, Apr. 2000, pp. 70-77, vol. 33, Issue 4.
Matsumoto, Yohei et al., “Performance and Yield Enhancement of FPGAs with Within-die Variation using Multiple Configurations,”Proceedings of the 2007 ACM/SIGDA 15thInternational Symposium on Field Programmable Gate Arrays(FPGA'07), Feb. 18-20, 2007, pp. 169-177, Monterey, California, USA.
Sedcole, Pete et al., “Parametric Yield in FPGAs Due to Within-die Delay Variations: A Quantitative Analysis,”Proceedings of the 2007 ACM/SIGDA 15thInternational Symposium on Field Programmable Gate Arrays(FPGA'07), Feb. 18-20, 2007, pp. 178-187, Monterey, California, USA.

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