Device having multiplexer for enabling priority and non-priority

Details Device having multiplexer for enabling priority and non-priority Device having multiplexer for enabling priority and non-priority

1988-02-24

1989-10-03

Williams, Jr., Archie E.

Boots, shoes, and leggings

3642281, 3642301, 3642427, 364238, G06F 946, G06F 1300, G06F 1318, G06F 1516

Patent

active

048721085

ABSTRACT:
A priority processor (1) and a non-priority processor (20) cooperatively access a common memory (30) by means of an address multiplexer (40) which memory and multiplexer are controlled by a control unit (60). The priority processor issues data strobe (DSSN), clock (CLK) and write control (WSN) signals to the control unit to which the non-polarity processor also issues various memory access request signals. By forming a preparation signal (DSSN=0), the priority processor, through the control unit, claims the memory for a memory access cycle if a prior memory access request by the non-priority processor occurred less than about a clock cycle earlier.

REFERENCES:
patent: 4096571 (1978-06-01), Vander May
patent: 4189766 (1980-02-01), Horiguchi et al.
patent: 4282572 (1981-08-01), Moore, III et al.
patent: 4422142 (1983-12-01), Inaba et al.
patent: 4594657 (1986-06-01), Byrns

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