Device having implantation for controlling gate parasitic action

Details Device having implantation for controlling gate parasitic action Device having implantation for controlling gate parasitic action

1978-03-06

1984-06-12

Clawson, Jr., Joseph E.

357 13, 357 51, 357 54, 357 59, 357 91, 357 2311, 357 235, H01L 2978

Patent

active

044545240

ABSTRACT:
A memory FET device having a channel implantation which controls gate parasitic transistor action. The parasitic action produces unwanted conduction paths which are formed in the transition regions between the thin memory oxide and the thick field oxide and extend along the sides of the gate region between the source and the drain. By blanket implanting through the oxide, which is relatively thin in the memory oxide region and increases in thickness across the transition region, and by adjusting the implant threshold, a continuous implant layer is formed which lies (1) within the field oxide, (2) at the substrate surface beneath the transition region oxide, and (3) deep within the body of the substrate beneath the gate region. The field oxide dopant and the substrate body dopant have no effect on the threshold voltage of the FET transistor channel, while the substrate surface doping under the transition region raises the threshold voltage of the parasitic device action to prevent interference with the operation of the FET. In a preferred embodiment, the device is MNOSFET.

REFERENCES:
patent: 3860454 (1973-06-01), DeWitt et al.
patent: 4029522 (1977-06-01), De La Moneda
patent: 4078947 (1978-03-01), Johnson et al.
patent: 4115794 (1978-09-01), De La Moneda
patent: 4143388 (1979-03-01), Esaki et al.
P. Krick, "The Implanted Stepped-Oxide MNOSFET," IEEE Trans. on Elec. Dev.," Feb. 1975, pp. 62-63.

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