Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including high voltage or high power devices isolated from...
Reexamination Certificate
2002-09-06
2004-12-21
Lee, Hsien-Ming (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including high voltage or high power devices isolated from...
C257S506000, C257S510000, C257S513000, C438S427000, C438S437000, C438S424000, C438S221000, C438S296000
Reexamination Certificate
active
06833602
ABSTRACT:
TECHNICAL FIELD
The present invention relates, in general, to semiconductor devices having low voltage and high voltage transistors and to processes for device fabrication and, more particularly, to electrical isolation for electrically-erasable-programmable-read-only-memory (EEPROM) devices and to process for fabricating electrical isolation structures.
BACKGROUND
Non-volatile memory devices are both electrically erasable and programmable. Such devices retain data even after the power to the device is terminated. One particular type of non-volatile memory device is the (electrically-erasable-programmable-read-only-memory) EEPROM device. In an EEPROM device, programming and erasing is accomplished by transferring electrons to and from a floating-gate electrode through a thin dielectric layer, known as a tunnel-oxide layer, located between the floating-gate electrode and the underlying substrate.
To program EEPROMs with a programmable logic device (PLD), a high voltage Vpp+ is applied to the gate electrode of the write transistor and a relatively lower voltage Vpp is applied to the drain (bit line contact) of the write transistor. The voltage applied to the write transistor gate electrode turns the write transistor on allowing the voltage applied to the bit line to be transferred to the source of the write transistor. The application of such high voltage levels is a write condition that results in a net positive charge being stored in the EEPROM cell.
To erase the EEPROM cell, a voltage Vcc is applied to the gate of the write transistor and ground potential is applied to the bit line and a high voltage Vpp+ is applied to the programming region. Under this bias condition, the high voltage applied to programming region is coupled to the floating-gate electrode and the EEPROM cell is erased by the transfer of electrons from the substrate to the floating-gate electrode.
The voltages required for programming and erasing of the EEPROM cell require charge pumping circuitry to generate the high voltages. In addition to charge pumping circuitry, other high voltage circuit elements include cell transistors, such as program transistors and sense transistors. An EEPPROM cell includes low voltage circuitry, such as read transistors and logic transistor. As in other types of devices, electrical isolation is necessary to electrically isolate various transistors in the device. In particular, it is necessary to electrically isolate the high voltage elements from the low voltage elements. Typically, low voltage devices require less robust isolation than high voltage devices.
To conserve valuable substrate area, the electrical isolation structure is fabricated by first forming a trench formed in the substrate. The trench is then filled with an electrically insulating material, such as silicon dioxide. The trench isolation runs between selected regions of the substrate containing, for example, the charge pumping circuitry and the EEPROM cells. The trench isolation also electrically separates active areas within the EEPROM cells. To adequately electrically isolate the high voltage devices, the trench needs to have a depth that is sufficient to contain a large amount of silicon dioxide. Conversely, only a relatively shallow trench is necessary to electrically isolate the low voltage devices. Simply making all of the isolation sufficient for the high voltage devices, however, consumes more substrate area than necessary. More compact, high-density device structures could be fabricated if an efficient method existed for fabricating trench isolation regions that were not excessively deep for isolation of low voltage device elements.
SUMMARY
The present invention relates to a process fabricating a semiconductor device having high voltage device elements and low voltage device elements. Although the invention is particularly suited to the fabrication of EEPROM devices, the electrical isolation structure and fabrication process of the invention can be used for any semiconductor device that includes high voltage and low voltage device elements.
In one aspect, a process for fabricating a semiconductor device includes providing a substrate having a principal surface and having a low voltage region and a high voltage region. A shallow portion of a low voltage isolation trench in the low voltage region and a shallow portion of a high voltage isolation trench in the high voltage region are simultaneously formed. Then, a deep portion of the high voltage isolation trench in the high voltage region is formed.
The deep portion provides electrical isolation between the high voltage region and the low voltage region. The shallow portion provides electrical isolation between adjacent portions of the low voltage region.
In another aspect of the invention, a process for fabricating isolation trenches in a substrate of a semiconductor device includes, for each of a plurality of isolation trenches, forming in the same process step, a shallow portion of sufficient depth to isolate a low voltage region, but not of sufficient depth to isolate a high voltage region. For an isolation trench that is to isolate a high voltage region, forming within the shallow portion, a deep portion of sufficient depth to isolate a high voltage region.
In another aspect a semiconductor device is provided that includes a substrate having a principal surface. The substrate also includes a low voltage region and a high voltage region. A trench having a deep portion and a shallow portion resides in the high voltage region, wherein the deep portion provides electrical isolation between the high voltage region and the low voltage region, and a trench resides in the low voltage region, wherein the shallow region provides electrical isolation between adjacent portions of the low voltage region.
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Wolf, “Silicon processing For The VLSI Era”; Vol. 3: The Submicron MOSFET; Lattice Press; 1995; pp 371-373.
Brinks Hofer Gilson & Lione
Lattice Semiconductor Corporation
Lee Hsien-Ming
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