Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Patent
1996-10-15
1999-10-05
Powell, Mark R.
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
348565, 348567, 348581, H04N 545, H04N 1393, G09G 500, G09G 514, G09G 536
Patent
active
059632216
ABSTRACT:
An input video signal is reduced according to size reduction ratio data K in an input processing section and written into alternate field memories. The written reduced video signal is alternately read from the field memories in a display processing section and processed for window displaying. Video reduction control sections are provided on the respective input and display sides, so that various signals, such as RHOLD, ADCANS, RACK signals, etc., are exchanged therebetween. When a size reduction ratio data K is changed, on the display side a read memory is fixed on a first field memory and size data is fixed, while on the write side video data is written into a second field memory, based on the new reduction ratio. After updating the size data on the display side, video data is read from the second field memory at the new reduction ratio. When reading and writing operations with respect to the second field memory are finished, fixing of the respective memories is released, whereby a signal processing operation returns to a normal operation.
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patent: 5510846 (1996-04-01), Guichard et al.
patent: 5517612 (1996-05-01), Dwin et al.
patent: 5557302 (1996-09-01), Levinthal et al.
patent: 5561472 (1996-10-01), Marietta et al.
patent: 5594467 (1997-01-01), Marlton et al.
Chida Kazunori
Shimizu Yutaka
Powell Mark R.
Rossi Jeffrey Allen
Sanyo Electric Co,. Ltd.
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