Electrical computers and digital processing systems: multicomput – Network-to-computer interfacing
Reexamination Certificate
1999-04-27
2003-05-20
Maung, Zarni (Department: 2154)
Electrical computers and digital processing systems: multicomput
Network-to-computer interfacing
C709S225000, C709S230000, C711S003000
Reexamination Certificate
active
06567859
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to the field of computer networking. More particularly, the present invention relates to the field of descriptors corresponding to a medium access control (MAC) device of a network interface card.
BACKGROUND ART
Computers have become an integral tool used in a wide variety of different applications, such as in finance and commercial transactions, computer-aided design and manufacturing, health care, telecommunication, education, etc. Computers are finding new applications as a result of advances in hardware technology and rapid development in software technology. Furthermore, a computer system's functionality is dramatically enhanced by coupling stand-alone computers together to form a computer network. In a computer network, users may readily exchange files, share information stored on a common database, pool resources, and communicate via electronic mail (e-mail) and via video teleconferencing.
One popular type of computer network is known as a local area network (LAN). LANs connect multiple computers together such that the users of the computers can access the same information and share data. Typically, in order to be connected to a LAN, a general purpose computer requires an expansion board generally known as a network interface card (NIC). Essentially, the NIC works with the operating system and central processing unit (CPU) of the host computer to control the flow of information over the LAN. Some NICs may also be used to connect a computer to the Internet.
Typically, NICs are also used to communicate over a LAN communications network standard referred to as Ethernet. When large amounts of data or data files are transmitted using Ethernet, a Transmission Control Protocol (TCP) segmentation process is typically run on a central processor unit (CPU) of a host computer in order to break the data down into transmission frames. For example, Ethernet has a maximum transmission frame size of 1514 bytes. Of the 1514 bytes of the transmission frame, there are a lot of bytes which are used for overhead. For instance, some bytes are used for addressing, other bytes are used for header information, etc. As such, the bytes remaining for the actual payload of data within each transmission frame are considerably less (e.g., 1460 bytes) than the 1514 bytes. It should be appreciated that there are disadvantages associated with this prior art process of segmenting data for transmission over a network.
One of the main disadvantages of this prior art segmentation process occurs as Ethernet network speed becomes ever faster (e.g., gigabit levels). At these high network speeds, the TCP segmentation process performed by the processor of the host computer becomes a bottleneck of the critical performance path, thereby slowing down the data throughput of the NIC. In other words, the processor becomes a bottleneck for data throughput of the NIC when used at high network speeds.
One of the prior art solutions for improving the throughput of the NIC is to implement an embedded processor onto the NIC in order to specifically perform the TCP segmentation process. In this manner, a large majority of the segmentation process is removed from the processor of the host computer and moved onto the embedded processor of the NIC. This prior art solution does improve the throughput of the NIC, but there are disadvantages associated with this prior art solution.
One of the main disadvantages of this prior art solution is that it does not effectively solve the problem of data throughput of a NIC when used with high speed networks (e.g., gigabit levels). Basically, the embedded processor of the NIC now becomes the bottleneck of the critical performance path thereby slowing down the data throughput of the NIC. In other words, the bottleneck for data throughput of the NIC is moved from the host processor to the processor of the NIC.
It should be appreciated that there is another disadvantage associated with the prior art TCP segmentation process, described above. As part of the prior art TCP segmentation process, descriptors are typically used to describe where particular data is stored within a memory device. The problem is that different descriptors are used for different medium access control (MAC) circuits which are part of a NIC. As such, a great majority of MAC descriptors are incompatible with different MAC circuits.
Accordingly, a need exists for a method and system for providing significantly improved data throughput of a network interface card which is used with a high speed network (e.g., gigabit levels). A further need exists for a method and system which meets the above need and provides a descriptor which can be tailored to a corresponding MAC device.
DISCLOSURE OF THE INVENTION
The present invention provides a method and system for providing significantly improved data throughput of a connection card which is used with a high speed network (e.g., gigabit levels). Moreover, the present invention provides a method and system which achieves the above accomplishment and provides a descriptor which can be tailored to a corresponding MAC device.
Specifically, one embodiment of the present invention includes a circuit for translating a medium access control descriptor from a first format into a second format. The circuit includes a translator circuit coupled to receive a descriptor which corresponds to data stored within a memory. Specifically, the translator circuit translates the descriptor from a first descriptor format into a second descriptor format. Furthermore, the circuit includes a medium access control (MAC) circuit coupled to the translator circuit to receive the descriptor in the second descriptor format. More specifically, the medium access control circuit uses the descriptor in the second descriptor format to retrieve the data from the memory.
In another embodiment, the present invention includes a circuit for translating a medium access control descriptor from a first format into a second format. The circuit includes a translator circuit coupled to receive a descriptor which corresponds to data stored within a local memory. The translator circuit translates the descriptor from a first descriptor format into a second descriptor format. Moreover, the circuit also includes a medium access control (MAC) circuit coupled to the translator circuit to receive the descriptor in the second descriptor format. The medium access control circuit uses the descriptor in the second descriptor format to retrieve the data from the local memory.
In still another embodiment, the present invention includes a method for translating a medium access control descriptor from a first format into a second format. The method includes the step of receiving a descriptor which corresponds to data stored within a memory. Furthermore, the method also includes the step of translating the descriptor from a first descriptor format into a second descriptor format. Additionally, the method includes the step of retrieving the data from the memory.
In yet another embodiment, the present invention includes the steps of the method described above and further includes the step of transmitting the data.
These and other advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the drawing figures.
REFERENCES:
patent: 5560038 (1996-09-01), Haddock
patent: 5748905 (1998-05-01), Hauser et al.
patent: 5758075 (1998-05-01), Graziano et al.
patent: 5937169 (1999-08-01), Connery et al.
Traber Rich
Yang Li-Jau (Steven)
3Com Corporation
Hu Jinsong
Maung Zarni
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