Excavating
Patent
1985-06-07
1988-03-08
Atkinson, Charles E.
Excavating
371 20, G01R 3128
Patent
active
047303190
DESCRIPTION:
BRIEF SUMMARY
The present invention relates to a device for transforming the occurrence probability of logic vectors and for generating vector sequences with time variable probabilities, applicable in particular to the production of a random testing device for logic circuits, particulary microprocessors.
In various domains of data processing, it is necessary to be able to have available, for particular applications, logic vector sequences with given probabilities. Such is for example the case of random testing devices for logic circuits such as microprocessors. In fact, to monitor logic circuits such as microprocessors, the functioning of two of these microprocessors, namely a reference microprocessor and the microprocessor subjected to the test, is compared. To this end, a sequence of instructions and orders is sent in parallel to the two microprocessors and a bit by bit comparison is made of the outputs of the two microprocessors. Any discordance appearing during such comparison makes it possible to detect a defect in the microprocessor subjected to the test.
It is an object of the present invention to procure a device for transforming the occurrence probability of logic vectors so as to produce, at the output of this device, vector sequences with given probabilities, from input vectors which may be equiprobable or themselves have different occurrence probabilities, this device advantageously being able to be used for the production of vector sequences with given probabilities applied to two logic circuits, in order to compare the functioning of one of these circuits with respect to another reference circuit.
To this end, this device for transforming the occurrence probability of logic vectors is characterized in that it comprises a memory or an equivalent circuit to which are applied input logic vectors having different or equal respective occurrence probabilities and containing, in respective areas of different ranges, the different categories of output vectors so that the occurrence probability of a determined output vector depends both on the range of the area of memory in which this vector is stored, i.e. on the number of elementary positions or eight bit bytes that this zone covers, and the respectives probabilities of the input vectors corresponding to the addresses of the elementary positions of the area of memory in question.
The invention also relates to a device generating sequences of vectors with time-variable probabilities, using at least one device for transforming the occurrence probability of logic vectors such as above mentioned characterized in that it comprises memories or equivalent circuits containing the different categories of vectors as well as the information necessary for identifying these different categories, and a sequencer based on logic circuits allowing the sequencing of the different types of vectors in time, as a function of given realtionships, the outputs of the memories or equivalent circuits being connected, via switches to one or more circuits adapted to receive them, such as for example microprocessors.
A particular application of the invention is constituted by a random testing device for logic circuits, particularly microprocessors, using at least one device for transforming the occurrence probability of logic vectors. This random testing device comprising a central unit, a generator of random sequences of instructions and orders applied in parallel to a reference microprocessor and to the microprocessor being tested, a comparator at the imputs of which are connected the data, address and monitoring outputs of each microprocessor and of which the output is connected to the central unit, is characterized in that the random sequence generator comprises a shift register looped as a sequence generator of maximum period by an exclusive OR circuit, the cells of the register corresponding to certain bits defined by a known mathematical property being connected to the inputs of the exclusive OR circuit, so that the shift register allows a pseudorandom generation of equiprobable vecto
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A. J. Walker, New Fast Method for Generating Discrete Random Numbers with Abitrary Frequency Distributions, Electronics Letters, vol. 10, No. 8, Apr. 18, 1974, pp. 127-128.
David Rene
Fedi Xavier
Atkinson Charles E.
Centre National de la Recherche Scientifique
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