Device for the self-synchronization of the output circuits of a

Details Device for the self-synchronization of the output circuits of a Device for the self-synchronization of the output circuits of a

1987-12-03

1989-11-07

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Sync/clocking

3652335, 36518908, 365154, 307473, G11C 800

Patent

active

048796930

ABSTRACT:
A self-synchronization device is disclosed for output circuits comprising a "3-state" gate of memories working in internal clock mode. This device consists of a sequential logic circuit which allows the "3-state" gate to go into low impedance only when a datum is available at the output of the read amplifiers.

REFERENCES:
patent: 4707810 (1987-11-01), Ferrant
patent: 4744063 (1988-05-01), Ohtani et al.
patent: 4761767 (1988-08-01), Ferrant
patent: 4771405 (1988-09-01), Burch et al.
patent: 4777623 (1988-10-01), Shimazu
IEEE Journal of Solid-State Circuits, vol. Sc-20, No. 5, Oct. 1985, pp. 941-950, IEEE, N.Y., U.S.; L. C. Sood et al.: "A fast 8K X 8 CMOS SCRAM with international power down design techniques"*Page 944, solonne de gauche, ligne 14--p. 945, colonne dedroite, ligne 8; FIGS. 6-12*

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