Metal working – Barrier layer or semiconductor device making – Barrier layer device making
Patent
1992-11-03
1994-05-24
Hearn, Brian E.
Metal working
Barrier layer or semiconductor device making
Barrier layer device making
29 2502, 437206, 437209, 437211, 437217, H01G 400
Patent
active
053136934
ABSTRACT:
The integrated circuit chips (5) are mounted on a ferrite support (20). The ferrite support is metallized uniformly (26) on its lower face and bears metallization zones (21, 24) on its other face. To certain of these zones (24) serving as a ground plane, there are attached the integrated circuit chips (5). The other zones (21) act as relays to connect the supply voltages that are applied by means of a linking wire (7') and a thin film decoupling capacitor (10, 11, 12) borne by the chip. The ground zones (24) are connected to the general ground plane (26) by metallized holes (25). The linking wire (7') is positioned so as to face a bared part of the ferrite to prevent any parasitic resonance.
REFERENCES:
patent: 5002895 (1991-03-01), LaParquier et al.
patent: 5023189 (1991-06-01), Bartlow
patent: 5063177 (1991-11-01), Geller et al.
patent: 5068714 (1991-11-01), Seipler
patent: 5200362 (1993-04-01), Lin et al.
"Thomson-CSF"
Hearn Brian E.
Picardat Kevin M.
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