Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Bipolar transistor
Reexamination Certificate
2002-04-12
2003-11-25
Nhu, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Bipolar transistor
C257S487000, C257S565000
Reexamination Certificate
active
06653669
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of analog and digital integrated circuits.
BACKGROUND OF THE INVENTION
It is desirable that analog and digital integrated circuits use as small an area of silicon as possible to reduce costs while maintaining high precision. The precision of eliminating circuits containing defects is excellent when the silicon wafers are sorted. However, this precision may deteriorate during the subsequent encapsulation step.
By way of example, offset voltages in an operational amplifier are on the order of 2 mV during wafer sorting which, after adjustment, are brought back down to 1 mV. However, packaging or encapsulation creates an additional shift bringing the final offset voltage back to 1.5 mV.
For a voltage reference or voltage regulator, the precision during wafer sorting is 0.8%, which is reduced to 0.2% after adjustment. As in the case of an amplifier, packaging introduces a shift bringing the final precision to 0.5%.
SUMMARY OF THE INVENTION
An object of the present invention is to adjust integrated circuits after they have been packaged, especially standard low-cost integrated circuits produced in high volume. A very high precision is to be obtained, which is at least equal to that obtained after adjustment during wafer sorting.
According to one aspect of the invention, the integrated electronic circuit comprises a resistor to be adjusted, an adjustment element mounted in parallel with the resistor to be adjusted, and at least one control transistor mounted between the adjustment element and a ground contact. The adjustment element comprises a MOS transistor, a first resistor placed between the substrate and the source of the MOS transistor, and a second resistor and a diode which are placed in series between the substrate and the drain. Both the gate and the source are short-circuited so that application of a voltage between the drain and the source biases the base/emitter junction of the parasitic bipolar transistor of the MOS transistor.
A breakdown of the MOS transistor is caused by an avalanche of the drain/substrate junction, an irreversible breakdown of the drain/substrate junction and a short circuit between the drain and the source. The element forms a resistor whose value is determined by the current due to the voltage.
A resistor may thus be adjusted independently of ground. In one embodiment of the invention, the circuit comprises a resistor in series with the resistor to be adjusted. The resistor includes a common terminal with the adjustment element. In one embodiment of the invention, the resistor to be adjusted is mounted with one terminal at a floating potential and another terminal is connected to the supply contact. In one embodiment of the invention, the control transistor is an NMOS transistor.
In one advantageous embodiment of the invention, the circuit comprises a first control transistor mounted between a supply contact and the adjustment element. A second control transistor is mounted between the adjustment element and a ground contact.
A resistor may thus be adjusted independently of ground and of the supply. In one embodiment of the invention, the resistor to be adjusted is mounted with two terminals at a floating potential. In one embodiment of the invention, the resistor to be adjusted is mounted with one terminal at a floating potential and another terminal is connected to the supply contact or to the ground contact. In one embodiment of the invention, the first control transistor is a PMOS transistor.
The second control transistor may be an NMOS transistor. The MOS transistor of the adjustment element may also be an NMOS transistor. However, a PMOS transistor may be used. Advantageously, the MOS transistor of the adjustment element includes an isolated structure. In one embodiment of the invention, the MOS transistor of the adjustment element is surrounded by a ring of p+-type conductivity. The ring may be surrounded by a well having a distance of greater than or equal to 20 &mgr;m.
In one mode of implementation of the invention, the application of a voltage between the drain and the source takes place before the circuit is encapsulated. In a preferred mode of implementation of the invention, the application of a voltage between the drain and the source takes place after encapsulating the circuit. The breakdown of the MOS transistor may be induced via the existing pins of the integrated circuit: ground, supply, input(s) and output(s). The voltage may be less than 10 volts, and is preferably less than 9 volts. The breakdown current may be less than 2 mA.
The base of the parasitic bipolar transistor is formed by the substrate, the collector is formed by the drain of the MOS transistor, and the emitter is formed by the source of the MOS transistor. The diode may be connected in such a way that it allows a current to flow from the drain to the substrate.
The present invention also provides a device for inducing the breakdown of a circuit as described above. The device comprises an analog/digital converter for the voltage applied to each input of the device, and generating means for generating a voltage for controlling a switch. The generating means is connected to the output of the converter, and a switch which is controlled by the generating means has one terminal connected to a supply and another terminal to be connected to the circuit.
Advantageously, the device comprises a reversible turn-off means capable of acting on the generating means. Advantageously, the device comprises an irreversible turn-off means capable of acting on the generating means. The turn-off means comprises a circuit that is able to breakdown. This turn-off means may be capable of turning off all the switches.
The circuit may comprise a diode such as a Zener diode, for example, or a transistor such as a MOS transistor, for example. The circuit may comprise a first resistor between the substrate and the source of a MOS transistor, and a second resistor and a diode in series between the substrate and the drain. The gate and the source are short-circuited so that application of a voltage between the drain and the source causes the base/emitter junction of the parasitic bipolar transistor of the MOS transistor to be biased. The MOS transistor breaks down by an avalanche of the drain/substrate junction, an irreversible breakdown of the drain/substrate junction and a short circuit between the drain and the source. The component forms a resistor having a value determined by the current due to the voltage.
The invention therefore makes it possible to provide standard integrated circuits with enhanced precision. The use of a so-called “snap-back” MOS transistor makes it possible to obtain a short circuit, and therefore to obtain a resistor within an integrated circuit after it has been encapsulated by acting on the existing pins of the integrated circuit. The component thus produced occupies only a small area on a silicon wafer since it comprises only one MOS transistor.
The fact that the gate and the source of the MOS transistor are short-circuited insures that it is permanently turned off, and prevents it from having any influence on the operation of the adjacent electronic circuits. Before breakdown, the component is like a turned-off MOS transistor. The diode makes it possible to avoid a leakage current during steady-state operation in those parts of the circuit to be adjusted, which in general, are operating at a voltage of a few millivolts. More generally, these parts of the circuit operate at a voltage below the threshold voltage of the diode.
The invention draws benefit from a natural characteristic of MOS transistors, which is to have parasitic components, particularly a bipolar transistor. In some configurations, these parasitic components are harmful. During electrostatic discharges circuits may be seriously damaged by the parasitic transistor being turned on.
On the other hand, the invention uses the parasitic bipolar transistor of the MOS transistor to make a short circuit to obtain a resistor having a pred
Laville Sébastien
Pontarollo Serge
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Nhu David
STMicroelectronics SA
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