Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
2000-06-28
2002-06-25
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Resistor
C438S383000, C257S328000, C257S335000
Reexamination Certificate
active
06410398
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of analog and digital integrated circuits. These circuits must use as small an area of silicon as possible to reduce costs while maintaining high precision.
BACKGROUND OF THE INVENTION
The precision of eliminating circuits containing defects is excellent during the step of sorting silicon wafers. However, this precision may deteriorate during the subsequent encapsulation step.
By way of example, offset voltages in an operational amplifier are on the order of 2 mV during wafer sorting which, after adjustment, are brought back down to 1 mV. However, packaging or encapsulation creates an additional shift bringing the final offset voltage back to 1.5 mV.
For a voltage reference or voltage regulator, the precision during wafer sorting is 0.8%, which is reduced to 0.2% after adjustment. As in the case of an amplifier, packaging introduces a shift bringing the final precision to 0.5%.
SUMMARY OF THE INVENTION
An object of the present invention is to adjust integrated circuits after they have been packaged, especially standard low-cost integrated circuits produced in high volume. A very high precision is to be obtained, which is at least equal to that obtained after adjustment during wafer sorting.
The process according to one aspect of the invention is intended for the formation of an electrical resistor in an integrated MOS transistor. A first voltage is applied to the source and the gate of the MOS transistor. A prebiasing voltage is applied to the substrate to make the base/emitter junction of a parasitic bipolar transistor of the MOS transistor conduct. A second voltage is applied to the drain of the MOS transistor. The first and second voltages are capable of initiating a breakdown of the MOS transistor by the following: an avalanche of the drain/substrate junction; an irreversible breakdown of the drain/substrate junction; and a short circuit between the drain and the source.
In one mode of implementation, the application of the first and second voltages takes place before the step of encapsulating a circuit that includes the MOS transistor. In a preferred mode of implementation, the application of the first and second voltages takes place after the step of encapsulating a circuit that includes the MOS transistor. The breakdown of the MOS transistor may be induced via the existing pins of the integrated circuit including ground pins, power supply pins, input pins, and output pins.
In another mode of implementation, one of the first and second voltages is constant and the other voltage is a monotonically changing ramp. In yet another mode of implementation, the first voltage is constant and the second voltage is a ramp. The ramp will be positive for an n-MOS transistor and vice versa for a p-MOS transistor. The difference between the first and second voltages may be less than 10 volts, and preferably less than 9 volts. The breakdown current may be less than 2 mA.
The present invention is also directed to an integrated electronic circuit provided with a MOS transistor. The integrated circuit comprises a first resistor placed between the substrate and the source of the MOS transistor, and a second resistor and a diode placed in series between the substrate and the drain. The gate and the source are short-circuited so that application of a voltage between the drain and the source biases the base/emitter junction of the parasitic bipolar transistor of the MOS transistor. The MOS transistor breaks down by the following: an avalanche of the drain/substrate junction, an irreversible breakdown of the drain/substrate junction, and a short circuit between the drain and the source. The resistive value of the component forming a resistor for the MOS transistor is determined by the current due to the voltage.
The base of the parasitic bipolar transistor is formed by the substrate, the collector is formed by the drain, and the emitter is formed by the source. The diode may be connected in such a way that it allows a current to flow from the drain to the substrate.
The present invention is also directed to an induction device for inducing the breakdown of a circuit as described above. The device comprises an analog/digital converter for the voltage applied to each input of the device, and a generating circuit or means for generating a voltage for controlling a switch. The generating means is connected to the output of the converter. A switch controlled by the generating means has one terminal connected to a supply and another terminal connected to the circuit.
Advantageously, the device comprises a reversible turn-off circuit or means capable of acting on the generating means. Advantageously, the device also comprises an irreversible turn-off circuit or means capable of acting on the generating means. The turn-off means comprises a circuit that is able to break down, and may be capable of turning off all the switches.
The circuit may comprise a diode such as a Zener diode, for example, or a transistor such as a MOS transistor, for example. The circuit may also comprise a MOS transistor. The circuit may comprise a first resistor between the substrate and the source of the MOS transistor. The circuit may comprise a second resistor and a diode in series between the substrate and the drain, with the gate and the source being short-circuited so that the application of a voltage between the drain and the source causes the base/emitter junction of the parasitic bipolar transistor of the MOS transistor to be biased. The MOS transistor breaks down by avalanche of the drain/substrate junction, the irreversible breakdown of the drain/substrate junction, and a short circuit between the drain and the source. The component forms a resistor having a value defined by the current due to the voltage.
The invention therefore makes it possible to provide standard integrated circuits with enhanced precision. The use of a so-called “snap-back” MOS transistor makes it possible to obtain a short circuit, and therefore obtain a resistor within an integrated circuit after it has been encapsulated by acting on the existing pins of the integrated circuit.
The component thus produced occupies only a small area on a silicon wafer in the sense that it comprises only one MOS transistor. The fact that the gate and the source of the MOS transistor are short-circuited ensures that it is permanently turned off and prevents it from having any influence on the operation of the adjacent electronic circuits.
After breakdown, the component may be likened to a turned-off MOS transistor. The diode makes it possible to avoid a leakage current during steady-state operation in those parts of the circuit to be adjusted. These parts of the circuit in general are operating at a voltage of a few millivolts, and more generally, at a voltage below the threshold voltage of the diode.
The invention draws benefit from a natural characteristic of MOS transistors, which is to have parasitic components, particularly a bipolar transistor. In some configurations, these parasitic components are harmful. During electrostatic discharges, circuits may be seriously damaged by the parasitic transistor being turned on.
On the other hand, the present invention uses the parasitic bipolar transistor of the MOS transistor to make a short circuit and obtain a resistor of predetermined value between the drain and the source of the MOS transistor. That is, between the collector and the emitter of the parasitic bipolar transistor. This component may be regarded as an anti-fuse. This is because a fuse is a closed circuit in the normal state and an open circuit after breakdown. Here, the component is an open circuit before breakdown (turned-off MOS transistor) and a closed circuit after breakdown with a low residual resistance value.
REFERENCES:
patent: 5539327 (1996-07-01), Shigehara et al.
patent: 6169309 (2001-01-01), Teggatz et al.
Forel Christophe
Laville Sébastien
Pontarollo Serge
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Berry Renee R.
Jorgenson Lisa K.
Nelms David
STMicroelectronics S.A.
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