Device for testing a circuit comprising sequential and combinato

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324 73R, 371 27, G01R 3128

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active

044358067

ABSTRACT:
A device for processing digital signals includes combinatorial and sequential logic elements. For the testing of the device, a shift register can be formed from the sequential elements. A test pattern is applied thereto. The result of the processing of the test pattern is applied to the shift register. The output of the shift register is connected to a second shift register which forms a moving multibit sum pattern from a received series of result patterns by way of a feedback circuit to at least one Exclusive-OR-element. An output of the feedback circuit is connected to an input of the first shift register in order to apply a subsequent test pattern thereto. After completion of the test, the sum pattern formed is checked.

REFERENCES:
patent: 3582633 (1971-06-01), Webb
patent: 3739160 (1973-06-01), El-Hasan et al.
patent: 3761695 (1973-09-01), Eichelberger
patent: 3924181 (1975-12-01), Alderson
patent: 4176780 (1979-12-01), Sacher et al.
patent: 4285059 (1981-08-01), Burlage et al.
patent: 4317200 (1982-02-01), Wakatsuki et al.
H. J. Nadig, Testing a Microprocessor Product Using a Signature Analysis, 1978 Semiconductor Test Conference, Cherry Hill, N.J., Oct.-Nov. 1978, pp. 159-169.

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