Device for synchronizing system clock using detected synchromiza

Details Device for synchronizing system clock using detected synchromiza Device for synchronizing system clock using detected synchromiza

1994-01-21

1995-07-11

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

3701051, 3701101, 375356, 375357, H04J 306

Patent

active

054327911

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
This invention relates to a digital switching system for connection to a public telecommunications network via digital circuits.
2. Description of the Prior Art
There is an increasing trend towards the digitization of the public telephone network due to the many advantages that digital systems can offer, such as ease of switching, lower maintenance, quality and flexibility. With ISDN (Integrated Services Digital Network) digitization is being taken direct to the customer via a standard twisted pair that will offer a 192 kbps basic rate circuit, consisting of two 64 kbps bearer channels and one 16 kbps data channel (2B+D). With ISDN the customer has direct access to digital services without the need for the present analog link between the customer terminal and the central office.
With the advent of ISDN, there is a need for switching systems that can interface directly with basic rate circuits. Although digital switching systems have been in use for some years, such systems interface with the public network through conventional analog lines. The systems comprise a system clock and a data carrying bus, generally a 2,048 Mbps serial bus, known as an ST bus, which carries thirty-two channels per frame.
When such systems are connected to the public network by digital circuits, some means has to be found to synchronize the system clock to the clock rate of the connected digital channel so as to allow error-free data transfer to take place. Conventionally this is done by by comparing the phase of the system clock with the phase of the clock signals on the connected circuit at the circuit interface, i.e. the basic rate interface card. A phase status word (psw) is then generated to represent the phase difference between the circuit clock and the system clock. This phase status word is transmitted through the system bus to the common control unit, where software is used to extract the phase difference information from a phase status word. This information is then used to vary the rate of the system clock so as to minimize the phase difference and thereby bring it into synchronization with the clock signals on the digital circuit.
The problem with this system is that it requires considerable bandwidth to transport the phase status word to the system clock and substantial processing power in order to extract the phase information from the phase status words. Also, since high frequency circuits are required at the interface units in order to effect phase comparison, electromagnetic interference can be significant since it is hard to adequately shield the interface units.
A typical example of such a system is described, for example, in EP-0368123. It will be seen that in this system the clock signals are all trasmitting through the system bus with the consequential high overhead in bandwith and processing power.
An object of the present invention is to alleviate the aforementioned disadvantages.


SUMMARY OF THE INVENTION

According to the present invention there is provided in a digital switching system connectable to a public telecommunications network via any one of a plurality of digital circuits and comprising a control unit including system clock and a system bus for carrying data through the system, an arrangement for synchronizing said system clock with a selected digital circuit, comprising means for detecting a network synchronization signal on said digital circuit, means for routing said detected synchronization signal directly to said system clock, and means for bringing said system clock into synchronization with the detected synchronization signal routed thereto.
By routing the synchronization signals directly to the system clock, the complex circuits required to transport phase status words can be eliminated. Also, since no high frequency comparison is done at the interface unit, electromagnetic interference can be reduced because the high frequency circuits are located in the main control unit, where EMI shielding is much more effective. Only one hig

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patent: 4628493 (1986-12-01), Nelson et al.
patent: 4736393 (1988-04-01), Grimes et al.
patent: 5184348 (1993-02-01), Abdelmouttalib et al.
patent: 5274678 (1993-12-01), Ferolito et al.
patent: 5331667 (1994-07-01), Izumi

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