Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-07-28
2001-10-16
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C375S362000
Reexamination Certificate
active
06304113
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a device for synchronizing analog signals, and, more particularly, to several of these devices associated with several respective analog signals to coordinate the reference events of the signals.
BACKGROUND OF THE INVENTION
FIG. 1
schematically shows a conventional device for synchronizing a reference event of an analog signal. Generally, the device is further provided to convert the synchronized analog signal into a digital signal.
A programmable delay line
1
receives an analog signal DLI
1
, and provides a delayed analog signal DLO
1
to an analog-to-digital converter
3
. Analog-to-digital converter
3
provides digital samples D
1
at the rate of a clock signal CK0 generated by a phase-locked loop
5
. A programmable delay line
2
receives an analog signal DLI
2
and provides a delayed analog signal DLO
2
to an analog-to-digital converter
4
. Analog-to-digital converter
4
provides digital samples D
2
at the rate of clock signal CK0. Delay lines
1
and
2
are respectively programmed by control signals COM(&Dgr;) and COM(&Dgr;′) generated by a control signal
7
according to signals DLI
1
and DLI
2
.
In an example, the reference event is a zero crossing of the signal. Control circuit
7
is then provided to set delay lines
1
and
2
so that the zero crossing of signal DLI
1
is synchronized on the zero crossing of signal DLI
2
.
FIGS. 2A
to
2
D illustrate the operation of the device of FIG.
1
.
FIG. 2A
shows a periodic analog signal DLI that transits through 0 at a time t0′ advanced by a duration A with respect to a reference time t0.
FIG. 2B
shows signal DLI
2
. Signal DLI
2
transits through zero at time t0 delayed by a duration a with respect to reference time t0.
FIG. 2C
shows clock signal CK0 generated by phase-locked loop
5
. Reference time to is arbitrarily determined by a rising edge of clock signal CK0.
FIG. 2D
shows two sequences of digital values ANO1 and AN
0
2 sampled at the respective rising edges of signal CK0.
Control circuit
7
varies delays &Dgr; and &Dgr; introduced by the delay lines between signals DLO
1
and DLO
2
until the delay between the 0 crossing of signal DLO
1
and of signal DLO
2
is zero, or the smallest possible, according to what is enabled by the pitch of the delay line.
Although a circuit such as that in
FIG. 1
operates satisfactorily, it has significant disadvantages. In particular, a digital circuit including a programmable analog delay line can only be formed in a BICMOS technology, which is expensive.
The features of a delay line, and especially its pitch, can considerably change if the manufacturing process changes. These feature variations are not desirable.
Further, an analog delay line is a delicate element, any modification of which must be performed with the utmost care. This element is said to be uneasily portable from one integrated circuit manufacturing technology to another.
Finally, current techniques do not enable obtaining programmable delay lines having a pitch smaller than an order of one nanosecond.
SUMMARY OF THE INVENTION
The disclosed embodiments of the present invention provide a device for synchronizing a reference event of several analog signals, which can be made in a CMOS technology. Hence, the characteristics of which do not vary according to the manufacturing method.
Such a synchronization device is easily portable from one integrated circuit technology to another. In addition, the synchronization device has a pitch smaller than one nanosecond.
An embodiment of the present invention provide a device for synchronizing a reference event of an analog signal, which includes:
an analog-to-digital converter receiving an input signal,
a register receiving the converter output,
a phase-locked loop including an oscillator generating several phase-shifted clock signals of same period, a first clock signal clocking the register,
a multiplexer receiving the other clock signals on respective inputs, the output of which clocks said converter, and
an analysis circuit connected to control the multiplexer according to successive values of the register output.
According to an embodiment of the present invention, the oscillator includes an even number of balanced differential amplifiers connected in an oscillating ring, an output of an amplifier of odd rank providing the first clock signal, and the outputs of the amplifiers of even rank providing said other clock signals.
According to another embodiment of the present invention, the analysis circuit includes a memory for storing the successive values of the register, and a microprocessor for analyzing the successive values to determine the zero crossing times of the output signal of the register.
According to a further embodiment of the present invention, a circuit including several synchronization devices such as previously described is provided, using a single phase-locked loop and the same clock signals.
According to yet another embodiment of the present invention, a circuit for controlling a laser disk reader such as previously described is provided, in which each synchronization device receives an analog signal coming from a pick-up of the disk.
The foregoing features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.
REFERENCES:
patent: 5553104 (1996-09-01), Takashi et al.
patent: 5646968 (1997-07-01), Kovacs et al.
patent: 5838738 (1998-11-01), Zook
patent: 5978425 (1999-11-01), Takla
patent: 0 680 170 (1995-11-01), None
patent: 2 310 772 (1997-09-01), None
Batruni, Roy et al., “Mixed Digital/Analog Signal Processing for a Single-Chip 2B1Q U-Interface Transceiver,”IEEE Journal of Solid-State Circuits, 25(6):1414-1425, 1990.
Callahan Timothy P.
Galanthay Theodore E.
Luu An T.
Seed IP Law Group PLLC
STMicroelectronics S.A.
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