Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2005-11-04
2009-08-18
Wells, Kenneth B (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S157000
Reexamination Certificate
active
07576577
ABSTRACT:
In a symmetrical phase-lock loop (PLL) device, first (I1P1, I1P2) and second (I2P1, I2P2) pairs of switches are disposed between (i) first and second outputs of a symmetrical time/voltage conversion block and (ii) first and second inputs of a voltage processing block. In addition, third (I3P1, I3P2) and fourth (I4P1, I4P2) pairs of switches are disposed upstream of the first and second inputs of the phase comparator (PC). Control means control the opening/closing of the first to fourth pairs of switches, such that: (a) during a first phase (P1), a first clock signal (Clkref) is connected to the first input of the comparator, a second clock signal (Clkdly) is connected to the second input of the comparator, the first output of the conversion block is connected to the second input of the processing clock and the second output of the conversion block is connected to the first input of the processing block; and (b) during a second phase (P2), the first clock signal is connected to the second input of the comparator, the second clock signal is connected to the first input of the comparator, the first output of the conversion block is connected to the first input of the processing block and the second output of the conversion block is connected to the second input of the processing block, in order to compensate the static phase error.
REFERENCES:
patent: 5477177 (1995-12-01), Wong et al.
patent: 6111470 (2000-08-01), Dufour
patent: 6720799 (2004-04-01), Gupta
patent: 0 718 978 (1996-06-01), None
PCT International Search Report for Application No. PCT/FR2005/002756.
PCT Request.
“A 500MHz MP/DLL Clock Generator for a 5Gb/s Backplane Transceiver in 0.25 μm CMOS” by Wei, et al. in 2003 IEEE International solid-State Circuit Conference, Paper 26.
Brinks Hofer Gilson & Lione
Commissariat a l''Energie Atomique
Rojas Daniel
Wells Kenneth B
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