Device for speeding up the reading of a memory by a processor

Details Device for speeding up the reading of a memory by a processor Device for speeding up the reading of a memory by a processor

1995-05-25

1997-11-11

Robertson, David L.

Static information storage and retrieval

Magnetic bubbles

Guide structure

395484, 39542109, 36523002, G06F 1300

Patent

active

056873417

ABSTRACT:
The device embodying the invention uses at least two read-only memory blocks containing the instructions of the application code and of which the addressing inputs are respectively connected to two counters connected to the address bus of the microprocessor. The read outputs of these blocks are connected to the data bus of the microprocessor via two buffers. A control circuit is provided to control, as a function of the nature of the addresses transmitted on the address bus and at the rhythm of the latter, a succession of cycles each comprising the transfer on the data bus, via one or other of the buffers, of the data contained in one or other of the memories and the incrementing of the counter associated with the other memory, in order to anticipate the data transfer of the next cycle. The invention applies notably to the processors taken on board aerodynes.

REFERENCES:
patent: 3771145 (1973-11-01), Wiener
patent: 4394642 (1983-07-01), Currie et al.

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