Device for regulating the throughput of virtual circuits on an a

Details Device for regulating the throughput of virtual circuits on an a Device for regulating the throughput of virtual circuits on an a

1992-07-24

1993-02-23

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 60, H04J 324

Patent

active

051896729

ABSTRACT:
A device for regulating the throughput of virtual circuits carried by an asynchronous time-division multiplex transmission channel in which the incoming cells of an input asynchronous time-division multiplex channel (mtr) including a header containing a destination indicator which can be used as a virtual circuit identifier are routed to a cell memory (MT) comprising a . . . , MAn), each cell being stored in the virtual circuit buffer memory associated with the virtual circuit to which the cell belongs, and the outgoing cells of an output asynchronous time-division multiplex channel (mte) are read in the same virtual circuit buffer memories (MA1, MA2, . . . , MAn). Cells to be transmitted on the outgoing link are read from the buffer memories in an order such that the cells from the same virtual circuit buffer memory are spaced on average by at least an interval specifier to that virtual circuit.

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IEEE Journal on Selected Areas in Communications, vol. SAC-5, No. 8, Oct. 1987, pp. 1315-1326, IEEE, New York, US; M. G. H. Katevenis: "Fast switching and fair control of congested flow in broad-band networks".
IBM Technical Disclosure Bulletin, vol. 18, No. 6, Nov. 1975, pp. 1787-1788, New York, US; S. W. Friedman et al.: "Queuing technique for bandwidth allocation in a packet switched network".

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