Chemistry: electrical and wave energy – Apparatus – Coating – forming or etching by sputtering
Reexamination Certificate
1993-07-20
2001-02-20
McDonald, Rodney (Department: 1753)
Chemistry: electrical and wave energy
Apparatus
Coating, forming or etching by sputtering
C204S192320
Reexamination Certificate
active
06190518
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to radio frequency (rf) sputter etch systems and more particularly to a device configured upon a semiconductor wafer or upon the sputter etch system which reduces damage associated with the sputter etch.
2. Background of the Relevant Art
The process of sputtering and sputter-etching has been studied and used for many years. More recent advances in sputter technology has led to the use of rf power systems for driving the sputter electrode. See, e.g., B. Chapman, “Glow Discharge Processes,” J. Wiley and Sons, New York, N.Y., 1980, pp. 135-173. RF sputtering includes both the deposition of thin films or the removal of thin films. Depending upon whether the object is placed upon the cathode or anode, either deposition or etching of thin films can occur. RF sputtering is sometimes used for deposition or etching of insulators which cannot easily be performed using direct current (dc) techniques due to substrate and target charging. RF sputter deposition is widely used for insulators such as silicon dioxide, aluminum dioxide, and/or other oxides where the substrate temperature limits preclude other techniques. Conversely, sputter etching is often used for pattern transfer, but because sputter etching is a high-energy process, it is rarely used for patterning thick films, except where the energy requirements can be lowered using chemical reaction (RIE) techniques.
Sputter etching using rf power is sometimes used to remove surface oxides in contact areas prior to metal sputter deposition. This has been shown to be effective for making low-resistance contact between successive aluminum thin-film wiring layers on semiconductor devices. Accordingly, second metallization layers can make good electrical contact to underlying layers due to the effective removal of native oxides which naturally grow within the contact areas prior to deposition. See, e.g., Rossnagel, S., et al., “Handbook of Plasma Processing Technology,” Noyes Publ., Park Ridge, N.J., 1990, pp. 154-157.
It is well recognized that rf discharges generally occur at relatively high voltage (600-1500 volts) and at high frequency (13.56 MHz). Plasma is formed near the wafer surface by breakdown of the gas within the sputter etch chamber. Electrons are repelled from the insulating layer (i.e., from the native oxide within the contact area) for most of the rf cycle, resulting in a positive time-averaged space charge. However, the cathode is usually smaller than the anode so that a high negative dc bias is developed on it with respect to the plasma. The cathode electrode and electrically connected wafer is bombarded at high energy by ions within the plasma during the negative portion of the applied voltage, and by electrons during the positive portion of the applied voltage. The resulting flow of ions and electrons during each cycle must be equal in order to preserve necessary charge neutrality. The electrons, being highly mobile, can easily provide enough charge over a small fraction of the cycle to neutralize the positive ion charge which flows during a majority of the cycle.
The bombardment of high energy ions upon the insulating layer dislodges atoms from the layer which are then accelerated by an applied electric field toward what is commonly called a “catcher plate” placed within the etch chamber. The catcher plate functions similar to an anode and preferrably has deep cavities similar to a honeycomb structure, and also should be well grounded with low-conductance, wide straps or foils to prevent self-bias.
Although plasma etching using rf sputtering techniques is well suited to provide fine-line removal of native oxides in an anisotropic fashion, there are many disadvantages associated with plasma etch as reported in Singer, P., “Evaluating Plasma Etch Damage,”
Semiconductor International,
May, 1992, pp. 78-81. Sputter etch can cause significant damage to the active regions within a semiconductor wafer. As defined herein, “active regions” refer to areas within a semiconductor having elements which can be activated in order to perform the specified functions of the integrated circuit defined thereon. Thus, active regions include those regions having passive or active elements (capacitors, resistors, transistors, etc.) necessary to carry forward the operation of the integrated circuit. Conversely, “inactive regions” are those regions which are defined outside the active regions and do not provide direct functionality of the integrated circuit. Generally, inactive regions are formed outside the die or integrated circuit area. Inactive regions, found near the outer periphery of the wafer, are generally unsuitable for accommodating an entire die. Inactive regions are usually discarded after the die are scribed and removed from the wafer. As described in the article to Singer, plasma etch can induce damage within the active area and may cause (i) gate oxide breakdown, (ii) high reverse leakage current, (iii) low minority carrier lifetime, (iv) foreign matter contamination of the silicon surface, (v) short order crystalline damage of the silicon surface, and (vi) radiation and lattice damage contamination from resist etch residues. The damage can result in skewed current-voltage transconductance, skewed flat-band voltage, and skewed threshold voltage, all of which are described in the Singer article.
It is possible to erase the effects of the damage caused by plasma etch by using a subsequent thermal annealing process. Annealing requires either a gradual or rapid heating of the wafer substrate in order to, inter alia, realign the interstitual defects caused by high energy ion bombardment. In many instances, rapid thermal anneal (RTA) requires temperatures exceeding, for example, 800° C. or 900° C. After a first metallization layer is deposited, and native oxides are sputter etch removed to allow contact with subsequent metallization layers, annealing can no longer be used to erase the deleterious effects of the sputter etch. After first metallization is placed, any subsequent annealing may melt or reflow the first metal causing problems such as poor step coverage, pin holes, hillocks etc. Thus, it is important that plasma etching after the first metallization be carefully controlled in order that damage does not occur since thermal anneal is not longer a suitable option for removing the damage at this stage of semiconductor process. It is important therefore that the plasma etch process be controlled in situ so that the source of wafer surface damage is minimized.
Referring now to the drawings,
FIG. 1
illustrates an exemplary conventional rf sputter etching system
10
similar to that shown in U.S. Pat. No. 4,298,443 (herein incorporated by reference). System
10
includes an etching chamber
12
and, placed within chamber
12
, is a holder
14
. Holder
14
includes a plurality of flat surfaces or facets, each facet is designed to receive a plurality of wafers
16
. Each wafer is held in place within aperatures
26
located within a front plate
18
by one or more clips or retainers
20
. Front plate
18
constitutes an anode which can be fixedly secured to one facet of holder
14
via clamp
22
. Retainers
20
firmly hold each wafer
16
in place against a cathode
24
during times in which plate
18
is secured to holder
14
. Cathode
24
is adapted to receive rf power as well as sufficient cooling media necessary to electrically bias the surface of wafer
16
which is brought in electrical contact therewith, and also to cool the wafer during high energy ion bombardment.
Turning now to
FIG. 2
, a more detailed view of front plate
18
is illustrated. Plate
18
includes a plurality of aperatures
26
, each of which sized to accommodate wafer
16
. When placed upon holder
14
, cathode
24
electrically abuts against the backside surface of wafer
16
to form a conductive path to the substrate of wafer
16
.
FIG. 2
illustrates four retainers
20
which clamp around the outer lip of wafer
16
as will be described further hereinbelow. Retainer
20
Goodwin Tom J.
Lowell John K.
Phan Tony T.
Advanced Micro Devices , Inc.
Conley Rose & Tayon
Daffer Kevin L.
McDonald Rodney
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