Device for rapid simulation of logic circuits

Details Device for rapid simulation of logic circuits Device for rapid simulation of logic circuits

1998-02-02

2000-06-06

Teska, Kevin J.

39550035, G06F 9455

Patent

active

060729481

ABSTRACT:
A logical simulation device has a delay value calculations section to calculate delay values of circuit blocks in a semiconductor integrated circuit as a target of logical simulation based on logical circuit information relating to the logical circuit blocks, input test patterns as operational descriptions of used in circuit verification, and delay value calculation information stored in a delay value and timing check value calculation library, and a logical simulation section performs the logical simulation of the semiconductor integrated circuit based on the calculated delay values.

REFERENCES:
patent: 5084824 (1992-01-01), Lam et al.
patent: 5548539 (1996-08-01), Vlach et al.
patent: 5623418 (1997-04-01), Rostoker et al.
patent: 5802349 (1998-09-01), Rigg et al.
patent: 5867399 (1999-02-01), Rostoker et al.
patent: 5880967 (1999-03-01), Jyu et al.

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