Device for protection against the formation of parasitic transis

Details Device for protection against the formation of parasitic transis Device for protection against the formation of parasitic transis

1990-07-17

1992-07-21

Pellinen, A. D.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 91, 357 48, 307303, H02H 904

Patent

active

051328666

ABSTRACT:
A monolithic integrated circuit (M) includes a power device (Q3, Q4) for driving an inductive load (L) and a control device for the power device. The control device comprises a voltage limiting circuit which includes a first transistor (Q2) responsive to negative impulses of the supply voltage and a second transistor (Q5) which is controlled by the first transistor for controlling re-firing of the power device in case of a negative pulse of the power voltage during a quenching period of the power device. The monolithic integrated circuit includes a substrate (5) having a substrate surface forming a supply voltage terminal of the power device and having a substrate voltage. An annular pocket (40) is formed in the substrate to surround or at least partially contain at least the first transistor (Q2) of the voltage limiting circuit. According to differing modes of the invention, the annular pocket (40) is biased at a voltage depending on that of the supply voltage terminal of the power device; is left at a floating potential. In one embodiment a pocket (3) is surrounded by an area of a different conductivity type (70) which has a grounded contact distributed along an emerging portion thereof.

REFERENCES:
patent: 3931634 (1976-01-01), Knight
patent: 4466011 (1984-08-01), Van Zanten
patent: 4679112 (1987-07-01), Craig
patent: 4775912 (1988-10-01), Menniti et al.
patent: 4845420 (1989-07-01), Oshizawa
patent: 4949212 (1990-08-01), Lenz et al.
patent: 5051612 (1991-09-01), Agiman

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