Device for programmable frequency divider

Details Device for programmable frequency divider Device for programmable frequency divider

2005-10-25

2005-10-25

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

Reexamination Certificate

active

06959066

ABSTRACT:
The present invention relates to a programmable frequency divider having one n-bit adder and one n-bit D Flip Flop. These are used to transform the import clock to the target clock. The adder takes one adjustment parameter and one return signal as a basis to create the first output signal, with the possibility to program the adjustment parameter. The D Flip Flop and the adder create a cycle, which is used to receive the first output signal and its import clock to create the second output signal. The second output signal is separated into a return signal and the target signal. The D Flip Flop sends the return signal back to the adder, which will make addition calculations under the adjustment parameter, finally giving out the target clock with the target signal as a calculation basis.

REFERENCES:
patent: 6084484 (2000-07-01), Chang et al.
Tro H. Nagle, “An Introduction to Computer Logic”, 1975, Prentice-Hall, pp. 236-238.

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