Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1992-06-11
1994-02-15
Sikes, William L.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307219, 3072723, 307517, 328111, H03K 513, H03L 700
Patent
active
052870103
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a device for preventing erroneous operation of a controller using a clock for its internal control when the clock is interrupted.
BACKGROUND ART
FIG. 9 shows a concept of an arrangement of a controller which performs its internal control based on a clock pulse as a reference generated at intervals of a constant time to controllably drive actuators.
As shown in the drawing, when a control signal including control data for driving of actuators 201 and 202 is applied to a controller 100, a data processing unit 101 in the controller extracts the control data from the received control signal and outputs it to an output signal latching circuit 102. During this operation, the data processing unit 101 is operated in synchronism with a clock pulse signal received from a clock generating unit 104. The latching circuit 102 latches the received control data and outputs the latched control data to an interface circuit 103. During this operation, the latching circuit 103 is similarly operated in synchronism with the clock pulse signal received from the clock generating unit 104. The interface circuit 103 subjects the input signal to a predetermined Level conversion and outputs the converted control data to the actuators 201 and 202 to controllably drive these actuators 201 and 202. Assume that the latching circuit 102 is made up of such a sequential circuit as, for example, a D flip-flop.
However, there sometimes occurs that the output of the clock pulse from the clock generating unit 104 is interrupted. This causes the subsequent clock pulse signal to remain at its logical level "0". Accordingly, when the output of the latching circuit 102 (D flip-flop) prior to the interruption of the output of the clock pulse remains at its logical level "1", the logical level "1" is maintained even after the stoppage of the output of the clock pulse. This results in that the interior of the controller is riot normally operated so that the actuators 201 and 202 become uncontrollable.
Therefore, the safety of the system will be remarkably deteriorated.
Also shown in FIG. 10 is a concept of an arrangement of a serial control system in which nodes (which will be referred to as the controllers, hereinafter), which respectively perform their internal controlling operation based on a clock pulse generated at intervals of a constant time to detect sensor signals and/or controllably drive associated actuators, are connected in a daisy chain form.
A data processing unit 103' in a controller 100' shown in the drawing generates control data for control of driving operation of a group of actuators 105' and outputs it to an interface circuit 104'. During this time, the data processing unit 103' is operated in synchronism with a clock pulse signal received from a clock generating unit 102'. The interface circuit 104' subjects the input signal to a predetermined level conversion, and outputs the converted control data to the group of actuators 105' to controllably drive these actuators 105'. And a clock pulse signal CK issued from the clock generating unit 102' as well as a data signal DT subjected at the data processing unit 103' to the data processing operation are transmitted through respective signal lines 400' and 500' to respective data processing units 203' and 303' of controllers 200' and 300' of the next and subsequent stages. In this case, the data processing unit 203' of the controller 200' receives the aforementioned clock pulse signal CK and data signal DT to operate in synchronism with the received clock pulse signal CK. That is, the data processing unit adds the received data signal DT to detection data from a group of sensors 205' through an interface circuit 204'. On the other hand, the data processing unit 303' of the controller 300' similarly receives the clock pulse signal CK and the data signal DT transmitted through the controller 200' to operate in synchronism with the received clock pulse signal CK, so that the data processing unit 303' controllably drives a group of actua
REFERENCES:
patent: 3634869 (1972-01-01), Hsuch
patent: 3772534 (1973-11-01), Dellecave et al.
patent: 3997798 (1976-12-01), Breimesser
patent: 4329652 (1982-05-01), Higa et al.
patent: 4600944 (1986-07-01), Williams
patent: 4633097 (1986-12-01), DeWitt
patent: 4763025 (1988-08-01), Takeuchi
Cunningham Terry D.
Hagiwara Masao
Sikes William L.
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