Multiplex communications – Diagnostic testing – Path check
Reexamination Certificate
1998-04-15
2002-03-26
Chin, Wellington (Department: 2664)
Multiplex communications
Diagnostic testing
Path check
C370S412000, C370S462000, C370S503000, C370S507000
Reexamination Certificate
active
06363054
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to circuits for connecting communication lines with a terminal, and particularly relates to a circuit which connects communication lines with a terminal when a point-to-multipoint connection is established in a communication system such as a SDH-ring system.
2. Description of the Related Art
FIG. 1
is an illustrative drawing showing an example of an SDH-ring system. The SDH-ring system of
FIG. 1
includes communication lines (SDH ring)
500
, a plurality of LSIs
501
, and a plurality of terminals
502
connected to the communication lines
500
via a corresponding one of the LSIs
501
. The LSIs
501
receives data transmitted via the communication lines
500
, and outputs the data to the terminals
502
. The terminals
502
are devices such as a PBX, an ISDN-TD, or the like, to which a telephone, a TV set, etc., can be connected.
The simplest configuration to achieve a point-to-multipoint connection is to use a fixed communication baud rate in each of the terminals
502
. In order to have simultaneous communication with as many terminals
502
as possible, the communication lines
500
must be provided with channels in the same number as the number of terminal channels defined by a terminal format.
In detail, a frame pulse XHF
0
/
1
is used for indicating a start timing of each frame of communication data, and a HW (highway:communication line) clock HWC
0
/
1
is used for establishing synchronization with a plurality of time slots contained in each frame. Each time slot is comprised of 8-bit data, and 32 time slots, for example, together make up one frame. In one frame, one or more time slots are put together to form a channel. When a communication baud rate is fixed and 8 channels are present, for example, each channel is comprised of 4 time slots. Each channel is called a path, and each path is used for communicating with a corresponding one of the terminals. Within one frame, an order of the path is not restricted but free to be set, and the order can be path
1
, path
7
, path
3
, path
5
, . . . , and so on, for example.
The start timing of each path on the side of the communication lines
500
is indicated by an offset number which is obtained by counting the number of pulses of HW clock HWC
0
/
1
from the timing of the frame pulse XHF
0
/
1
. This offset number is stored in a register inside each LSI
501
. In the case of a fixed communication baud rate, therefore, a fixed number of time slots starting from a timing indicated by the offset number are read from the communication lines
500
, and are output to the terminal. Namely, when the communication baud rate is fixed to four time slots, for example, arrival of the path
1
results in writing data in addresses
0
through
3
of the output to the terminal, and the arrival of the path
3
leads to writing data in addresses
8
through
11
. Such processing is conducted with regard to each path so as to output each path in a predetermined order to the terminal
502
. In this case, the LSI
501
can be implemented by using a simple configuration.
When a communication baud rate is different for each path, however, the number of time slots varies for different paths. In this case, a simple process as described above is not applicable when paths arranged in an order of free choice on the side of the communication lines
500
need to be output to the terminal
502
in the order of path numbers. The communication baud rate (the number of time slots) of each path is stored in the register inside the LSI
501
, as described above. The communication baud rate thus may be decoded with respect to each path so as to control a position of data writing, so that data of each path is written at an appropriate address position in the output to the terminal. Such a process, however, requires a complex and large circuit structure, resulting in an undesirable enlargement of a circuit size of the LSI
501
.
Accordingly, there is a need for a small-scale circuit which can output data of paths to the terminal by using a simple process when the paths are provided in an order of free choice on the side of the communication lines in a system employing a point-to-multipoint connection and an adjustable communication baud rate.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a small-scale circuit which can satisfy the need described above.
It is another and more specific object of the present invention to provide a small-scale circuit which can output data of paths to the terminal by using a simple process when the paths are provided in an order of free choice on the side of the communication lines in a system employing a point-to-multipoint connection and an adjustable communication baud rate.
In order to achieve the above objects according to the present invention, a device for outputting paths to a terminal after rearranging the paths when the paths are arranged in an order of free choice on a side of communication line includes a counter which receives a path number of a path in response to first data of the path, and counts up a count starting from the path number in response to second and following data of the path. The device further includes a storage unit which stores real data of the path at positions indicated by the count, wherein the real data stored in the storage unit is output to the terminal.
In the device described above, the real data of the path is written at positions controlled by the counter, so that terminal-side output is obtained such that the real data of path n holds an output position thereof in the n-th and following time slots. In this manner, a simple process and a simple circuit based on path numbers can rearrange communication-line data into terminal-side data.
According to one aspect of the present invention, the device further includes a data-enable circuit which holds 1 at positions therein indicated by the count when the real data is written at the positions indicated by the count in the storage unit, wherein the data-enable circuit holds zero at all positions therein at an initial state with respect to each frame.
In the device described above, the data “1” is set in the data-enable circuit so as to correspond, in terms of positions thereof, to the read data output to the terminal. In this manner, data for indicating a valid/invalid status of each time slot can be readily obtained with regard to the real data output to the terminal.
According to another aspect of the present invention, the device further includes a circuit which masks the real data output to the terminal by using data held in the data-enable circuit.
In the device described above, a valid/invalid status of each time slot can be found by using the data-enable circuit, so that invalid data can be masked so as not to be output.
According to another aspect of the present invention, the device further includes control-information-allocation circuit which receives control information allocated to the paths, and outputs the control information to the terminal in synchronism with the real data output to the terminal.
In the device described above, control information such as error information contained in paths can be output to the terminal in synchronism with the real data.
According to another aspect of the present invention, the control-information-allocation circuit includes a plurality of selectors which are connected in series such that one of the selectors receives as one of inputs thereof an output from a preceding one of the selectors.
In the device described above, the circuit comprised of the plurality of selectors can allocate the control information.
According to another aspect of the present invention, each of the plurality of selectors selects either the output from the preceding one of the selectors or the control information on a corresponding path, depending on whether a communication-data rate of the corresponding path is zero.
In the device described above, the circuit comprised o
Chin Wellington
Fujitsu Limited
Phan M.
Staas & Halsey , LLP
LandOfFree
Device for outputting communication-line data to terminal does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Device for outputting communication-line data to terminal, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device for outputting communication-line data to terminal will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2822290