Device for minimizing parasitic junction capacitances in an insu

Details Device for minimizing parasitic junction capacitances in an insu Device for minimizing parasitic junction capacitances in an insu

1988-02-08

1990-06-19

Clawson, Jr., Joseph E.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 40, 357 42, 357 51, 307246, 307254, 3072962, 307355, 307491, 330 85, 330307, H01L 2972

Patent

active

049357964

ABSTRACT:
A device for minimizing parasitic junction capacitances in an isolated collector vertical PNP transistor, having a terminal N connected to an epitaxial n layer, comprises a bootstrap circuit including an emitter follower vertical PNP transistor having its emitter and base respectively connected to the terminal of the epitaxial n layer and the collector of the isolated collector transistor; further, a bias resistance is connected between the emitter and one pole of a voltage supply to the emitter follower.

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