Device for loading and reading strings of latches in a data proc

Details Device for loading and reading strings of latches in a data proc Device for loading and reading strings of latches in a data proc

1983-09-19

1986-06-24

Eng, David Y.

Boots, shoes, and leggings

371 25, 324 73R, G06F 1100, G01R 3128

Patent

active

045970424

ABSTRACT:
A device for loading data in and reading data out of latch strings located in field replaceable units containing the circuitry of a data processing system realized in accordance with the Level-Scan Sensitive Design (LSSD) technique. Each field replaceable unit includes an addressing circuit. The addressing circuits are interconnected by a monitoring loop over which a configuration of address bits is serially transmitted by a control circuit. The data to be loaded and read out propagate in a data loop and are entered in a latch string under control of the addressing circuit.

REFERENCES:
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patent: 4023142 (1977-05-01), Woesmer
patent: 4030072 (1977-06-01), Bjornsson
patent: 4041471 (1977-08-01), Krossa et al.
patent: 4167041 (1979-09-01), Curlander et al.
patent: 4183461 (1980-01-01), Sato
patent: 4268902 (1981-05-01), Berglund et al.
patent: 4298980 (1981-11-01), Hajdu et al.
patent: 4326266 (1982-04-01), Davis et al.
patent: 4476431 (1984-10-01), Blum
"Design for Testability of the IBM System/38", L. A. Stolte & N. C. Berglund, 1979 IEEE Test Conference, Cherry Hill, NJ, pp. 29-36.
"Level-Sensitive Scan Design Tests Chips, Boards, System", N. C. Berglund, Electronics, Mar. 15, 1979, pp. 108-110.

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