Television – Receiver circuitry – Demodulator
Reexamination Certificate
1997-10-31
2002-07-02
Miller, John W. (Department: 2614)
Television
Receiver circuitry
Demodulator
C348S465000, C348S425100, C348S714000, C348S461000
Reexamination Certificate
active
06414726
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to circuitry of identifying packets of data to a receiver for digital television signals employing such circuitry.
BACKGROUND OF THE INVENTION
Currently, digital television signals are transmitted in a format known by the term MPEG.
According to this format, the signals are transmitted in the form of data packets, each comprising a useful signal and a header signal containing data pertaining to the contents of the useful signal.
A digital television signal generally consists of packets of various types, such as audio data packets, video data packets and packets containing information pertaining to the program transmitted.
In general, the decoding of television signals takes place in a decoder of a reception station, with the identification and the selection, in the incoming signals, of audio and video data packets and with the decoding of these packets so as to form data trains, of the audio and video types, respectively.
The audio data trains are decoded by means of an audio decoder for forming an analog acoustic signal.
Similarly, the video data trains are used to form an image as well as chrominance and luminance signals.
There are known devices for the identification of packets. These devices extract a piece of data from each header signal, which is representative of the type of the corresponding useful signal. They include a means for storing reference data in a memory, at addresses each corresponding to one packet type, and a means for comparing the piece of data extracted from each header signal with said reference data (stored in the memory) to deliver, to a data processing unit, an address signal indicating the nature of the corresponding packet.
The processing unit then selects the identified packets for decoding and for forming corresponding data trains.
In this type of identification device, the comparison between the piece of data extracted from the header signal and the reference data stored in memory is conducted successively; that is, at a transition of a synchronization clock, an extracted piece of data is compared to one of the reference pieces of data.
In addition, since the transmission rate of the packets is very high, the packet being identified must be stored, at least temporarily, for example, in a memory of the FIFO type, associated with a piloting circuit.
Consequently, this type of identification device is relatively slow and requires a large number of components.
The purpose of the invention is to overcome these drawbacks.
SUMMARY OF THE INVENTION
Circuitry for identifying digital data packets, each comprising a useful signal and a header signal containing data pertaining to the contents of the useful signal is provided. The circuitry includes a means (
30
) for extracting data from each header signal, which data is representative of a corresponding useful signal, a means for storing reference data in a memory, at addresses each corresponding to a packet type, and a means for comparing the data extracted from each header signal with said reference data stored in memory, and for the delivery, to a data processing unit (
32
,
34
), of an address signal indicating the nature of the corresponding packet. The data storage means and the comparison means preferably employ an associative memory (
38
) adapted to ensure the simultaneous comparison of the data extracted from each header signal with the reference data stored in memory.
An electronic device for identifying packets (
10
) of digital data, with each packet continuing a usefull signal (
14
) and a header signal (
12
) containing data about the contents of the useful signal (
14
) is provided that includes a means (
30
) for extracting a portion of data from each header signal, which is representative of the nature of the corresponding useful signal (
14
); memory storage means (
38
,
44
,
46
) for the reference data, at addresses each corresponding to one packet type; and comparison means (T
3
,T
4
,T
5
) for comparing the piece of data extracted from each header signal (
12
) with said reference data stored in memory and delivering data to a data processing unit (
32
,
34
) of an address signal indicating the type of the corresponding packet (
10
), wherein the memory storage means and the comparison means consist of an associative memory (
38
) adapted to ensure the simultaneous comparison of the piece of data extracted from each header signal with the reference data stored in memory.
REFERENCES:
patent: 5182799 (1993-01-01), Tamura et al.
patent: 5307343 (1994-04-01), Bostica et al.
patent: 5742361 (1998-04-01), Nakase et al.
patent: 5802063 (1998-09-01), Deiss
patent: 5898695 (1999-04-01), Fujii et al.
patent: 5960006 (1999-09-01), Maturi et al.
patent: 5966385 (1999-10-01), Fujii et al.
patent: 0 679 028 (1995-10-01), None
patent: 0 735 776 (1996-10-01), None
patent: 0 840 520 (1998-05-01), None
Fujii, et al.,Implementation of MPEG Transport Demultiplexer With a RISC-Based Microcontroller, IEEE Transactions on Consumer Electronics, U.S., IEEE Inc., NY, vol. 42, No. 3, Aug. 1, 1996, pp. 431-438.
Brady III W. James
Laws Gerald E.
Lo Linus H.
Miller John W.
Telecky , Jr. Frederick J.
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