Static information storage and retrieval – Addressing – Sequential
Reexamination Certificate
2000-07-28
2004-09-07
Peikari, B. James (Department: 2186)
Static information storage and retrieval
Addressing
Sequential
C711S219000, C365S230010, C365S189011, C365S189080, C365S189120, C365S236000, C365S230080
Reexamination Certificate
active
06788617
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a transposing memory, and more particularly, to a device that generates memory addresses.
2. Background of the Related Art
A transposing memory is used in an encoder, decoder, or an interleaver in a mobile communication system. For a mobile station having a picture transmission function, the encoder encodes a picture data for transmission of the picture to an opposite party, and the decoder receives and decodes the encoded picture data into an original picture data. The interleaver is provided for minimizing a burst error of the data transmitted in a CDMA type communication system.
The encoder and decoder of the mobile station will now be described.
FIG. 1
illustrates a block diagram showing a part of a related art encoder.
As shown in
FIG. 1
, the related art encoder is provided with a 2D DCT part
100
for receiving, and twice subjecting a picture data to Discrete Cosine Transform (DCT), a quantizing part
110
for receiving and quantizing the picture data from the DCT part
100
, and a zigzag scanning block
120
for scanning DC and AC components of the picture data quantized at the quantizing part
110
in a zigzag for encoding the DC and the AC components. A Variable Length Coding (VLC) part
130
is for assigning codes of short lengths to symbols with a high frequency of occurrences in view of probability, and assigning codes of long lengths to symbols with a low frequency of occurrences. A channel buffer
140
buffers the encoded picture data. An inverse quantizing part
150
is for subjecting the DCT data from the quantizing part
110
to inverse quantizing, and a 2D IDCT part
160
is for twice subjecting the DCT data from the inverse quantizing part
150
to Inverse Discrete Cosine Transform (IDCT).
The 2D DCT part
100
is provided with a first DCT
101
for receiving and subjecting the picture data to DCT, a transposing memory
102
for storing the DCT picture data in a row direction and presenting in a column direction and a second DCT
103
for subjecting the data from the transposing memory
102
to DCT. A row direction address generator
104
generates a writing address of the transposing memory
102
, and a column direction address generator
105
generates a reading address of the transposing memory
102
.
The 2D IDCT part
160
is provided with a first IDCT
163
for receiving and subjecting the DCT data from the inverse quantizing part
150
to IDCT, a transposing memory
162
for temporary storing the IDCT data in the row direction and presenting in a column direction and a second IDCT
161
for subjecting the data from the transposing memory
162
to IDCT. A row direction address generator
164
generates a writing address of the transposing memory
162
, and a column direction address generator
165
generates a reading address of the transposing memory
162
. The zigzag scanning block
120
is provided with a zigzag scanning part
121
for zigzag scanning the quantized data. A column direction address generator
122
and a zigzag address generator
123
provide a scanning and an output address to the zigzag scanning part
121
, respectively. A detailed description of the decoder will be omitted here as the decoder has a system opposite to the encoder.
The operation of the related art encoder will now be described. The picture data has a high correlation between adjacent data. Therefore, a two dimensional data operation, such as DCT, is processed by twice performing a one dimensional operation using orthogonal transform characteristics. Thus, the data subjected to a first one dimensional operation at the first DCT
101
is stored in the transposing memory
102
according to the writing address generated in the row direction at the row direction address generator
104
. The data stored in the row direction in the transposing memory
102
is presented by the reading address generated in the column direction at the column direction address generator
105
and subjected to a one dimensional operation for the second time at the second DCT
103
. The foregoing process is applicable to the IDCT process, except that the data is stored according to a writing address generated in the row direction at the transposing memory
162
in the 2D IDCT part
160
, and presented in the column direction according to a reading address generated in the column direction. In the meantime, the data is provided to the zigzag scanning part
121
according to the column direction writing address provided from the column direction address generator
122
. States of the picture data input to/output from the transposing memory
102
are shown in
FIGS. 2A and 2B
, respectively.
The column direction address generator in the related art encoder will now be described.
FIG. 3
illustrates row/column direction address generators shown in FIG.
1
.
As shown in
FIG. 3
, since the data from the transposing memory
102
or
162
has a transposed matrix, the column direction address generator is required to provide the reading address for presenting the data stored in the transposing memory
102
and
162
. Therefore, the column direction address generator
105
or
164
is provided with a first counter
300
for providing an 2
n
(i.e., 0, 1, 2, 3, 4, 5, 6, 7 when n=3) by up counting a pulse signal every time the pulse signal is provided to an enable terminal. An initial value generator
310
takes a new value from the first counter
300
as an initial value every time the new value is provided from the first counter
300
. A second counter
330
is for repeatedly counting 2
n
to generate a carry out signal whenever the count is 2
n
, and provide the carry out signal to the first counter
300
and the initial value generator
310
as an enable signal. Further, a step sizer
340
always provides 2
n
, and an accumulator
320
accumulates the 2
n
value from the step sizer
340
for 2
n
times using the signal from the initial value generator
310
as an initial value and then forwards the accumulated value.
The operation of the column direction address generator will now be described. As shown in
FIG. 4
, it is assumed that the transposing memory
102
or
162
is a square of 2
n
×2
n
. Thus, when the first counter
300
, the second counter
330
, and the initial value generator
310
are initialized, the first counter
300
provides ‘0’ so that the initial value generator
310
initializes the accumulator
320
at ‘0’ for the accumulator
320
to provide an address of ‘0’. Next, the accumulator
320
adds the 2
n
from the step sizer
340
to provide 2
n
. The accumulator
320
keeps adding 2
n
from the step sizer
340
in succession to provide repeatedly accumulated 2
n
values (2×2
n
, 3×2
n
, 4×2
n
, 5×2
n
, 6×2
n
, - - - , 2
2n
−2
n
) as addresses of a first column of the transposing memory
102
. Then, the second counter
330
, which provides a number of repetitions generates a carry out, and the first counter
300
is enabled by the carry out to provide ‘1’, and the initial value generator
310
initializes the accumulator
320
at ‘1’. Accordingly, the accumulator
320
provides ‘1’, and then the 2
n
from the step sizer
340
is repeatedly added to the ‘1’ from the accumulator
320
for 2
n
times to provide addresses of the second column (‘1’,1+2
n
, 1+2×2
n
, 1+3×2
n
, 1+4×2
n
, 1+5×2
n
, 1+6×2
n
, - - - , 1+2
2n
−2
n
). In the same manner, the first counter
300
provides 2, 3, 4, 5, 6, and 7, and the accumulator repeatedly accumulates the 2
n
from the step sizer
340
for 2
n
times whenever the first counter
300
provides the 2, 3, 4, 5, 6, and 7. Thus, the column direction address generator can generate column direction reading addresses for all columns of the 2
n
×2
n
transposing memory.
As described above, however, the related art encoder has various problems in the column direction address generator. First, the two counters and two accumulators in the relat
Fleshner & Kim LLP
LG Information & Communications Ltd.
Peikari B. James
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