Device for filtering positive dejustification jitter of a digita

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G06F 1531

Patent

active

055814930

ABSTRACT:
A device for filtering positive dejustification jitter of a digital bit stream includes a phase-locked loop for slaving the timing of a signal representative of the read timing of a buffer memory into which the dejustified digital bit stream is written to the timing of a signal representative of the write timing of the buffer memory. The device applies low-pass filtering and determines the actual justification rate of the digital bit stream and deduces therefrom the difference justification rate, i.e. the difference between the actual rate and a nominal justification rate of the digital bit stream. It systematically eliminates phase shifts due to positive dejustification from the signal representative of the buffer memory write timing, regenerates phase shifts of the signal in numbers corresponding to the nominal justification rate, and regenerates phase shifts of the signal in numbers corresponding to the difference justification rate and smooths the phase shifts.

REFERENCES:
patent: 5253118 (1993-10-01), Konno
patent: 5343476 (1994-08-01), Urbansky
patent: 5410499 (1995-04-01), Waters

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