Device for executing a program of instructions

Details Device for executing a program of instructions Device for executing a program of instructions

1995-10-25

1999-06-29

Eng, David Y.

G06F 940

Patent

active

059180307

ABSTRACT:
The device comprises 2.sup.n memories (Mi) or memory areas in parallel, among which the A instructions are distributed, a unit (UT) for processing these instructions and a management unit (DI, AC) sensitive to a jump instruction extracted from one of the memories in order to disrupt the ordered activation of memories and in its place to activate the memory containing the address given in the jump instruction, and to cause the instruction placed at this address to be delivered to the processing unit (UT). The n least significant bits (LSB) of said M-bit address identify the memory (Mi) or the memory area containing this address, while the (M-n) most significant bits (MSB) identify one of 2.sup.M-n rows of 2.sup.n addresses each taken from one of the 2.sup.n memories. The management unit a control automaton (AC) sensitive to the n (LSB) bits of the address in order to activate the memory containing said address and to cause the instruction which is located there, in the row identified by the (M-n) (MSB) bits, to be delivered to the processing unit.

REFERENCES:
patent: 4694407 (1987-09-01), Ogden
patent: 5127091 (1992-06-01), Boufarah et al.
"Machine Organization of the IBM Risc SyStem/6000 Processor", IBM Journal Research and Development, vol. 34, No. 1, Jan. 1990, pp. 37-58.
"Cache Organization to Maximize Fetch Bandwidth", IBM Technical Disclosure Bulletin, vol. 32, No. 2, Jul. 1989.
"DSNS (Dynamically-Hazard-Resolved, Statically-Code-Scheduled, Nonuniform Superscalar): Yet Another Superscalar Processor Architecture", Computer Architecture News, vol. 19, No. 4.

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