Device for evaluating the throughput of virtual circuits on an a

Details Device for evaluating the throughput of virtual circuits on an a Device for evaluating the throughput of virtual circuits on an a

1990-10-12

1992-07-07

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 60, 370 941, H04J 116, H04J 324

Patent

active

051289245

ABSTRACT:
The incoming cells of a input asynchronous time-division multiplex channel (mtr) are counted by a counter (FFB) assigned to each virtual circuit which is incremented on each incoming cell of the virtual circuit and decremented periodically. Clock signals define consecutively numbered cell times (ntc). Queue and chaining table (FAVE, FCVN) define a cell time queue (FAF, FAL, FAV) specific to each of the cell times, a virtual circuit being assignable to a cell time by writing its identifier into the corresponding cell time queue. A controller (MC) uses the content of the cell time queues (FAF, FAL, FAV) and, for each cell time, identifies a virtual circuit to be processed and decrements the counter (FFB) belonging to this virtual circuit. The controller further includes arrangements whereby any virtual circuit whose counter is not idle is assigned to one of the cell times to be decremented by virtue of the arrival of this cell time.

REFERENCES:
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patent: 4484326 (1984-11-01), Turner
patent: 4769810 (1988-09-01), Eckberg, Jr. et al.
patent: 4769811 (1988-09-01), Eckberg, Jr. et al.
patent: 4896316 (1990-01-01), Lespanol et al.
patent: 4993024 (1991-02-01), Quinguis et al.
patent: 5007048 (1991-04-01), Kowalk
IEEE Journal on Selected Areas in Communications, vol. SAC-5, No. 8, Oct. 1987, pp. 1315-1326, IEEE, New York, US; M. G. H. Katevenis: "Fast switching and fair control of congested flow in broadband networks".

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