Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-01-28
2002-06-18
Nguyen, Vinh P. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010, C324S719000
Reexamination Certificate
active
06407573
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a device for evaluating a characteristic of an insulated gate transistor which extracts the effective channel length and also the series resistance of the insulated gate transistor.
2. Description of the Background Art
The resistance-based method is intended for extracting a series resistance R
sd
and an effective channel length L
eff
. However, the resistance-based method determines a channel length reduction DL (=L
m
−L
eff
) in place of the effective channel length L
eff
where L
m
is a mask channel length (designed channel length). The resistance-based method carries out the extraction on the assumption that a total drain-to-source resistance R
tot
is the sum of the series resistance R
sd
and a channel resistance R
ch
. A relationship which holds between the effective channel length L
eff
and the channel resistance R
ch
is such that the channel resistance R
ch
is the product of the effective channel length L
eff
and a channel resistance f per unit length.
FIG. 24
conceptually shows the relationship between the channel resistance R
ch
, the series resistance R
sd
, the effective channel length L
eff
, the mask channel length L
m
, and the channel length reduction DL. The relationship shown in
FIG. 25
approximately holds between the total drain-to-source resistance R
tot
and the mask channel length L
m
. Specifically, with a gate voltage V
gs
or the gate voltage V
gs
minus a threshold voltage V
th
held constant, the total drain-to-source resistance R
tot
changes in constant proportion to the mask channel length L
m
. The gate voltage V
gs
minus the threshold voltage V
th
is referred to hereinafter as a gate overdrive V
gt
. It is assumed that R
tot−L
m
lines for various values of the gate overdrive V
gt
intersect at one point. The mask channel length L
m
coordinate of the point of intersection is represented by DL*, and the total drain-to-source resistance R
tot
coordinate thereof is represented by R
sd
*. The symbol * which follows the reference character representing a value indicates that the value is determined based on such a relationship which holds between the total drain-to-source resistance R
tot
and the mask channel length L
m
, in other words, based on characteristic curves plotted in the X-Y plane defined by an X-axis which denotes the mask channel length and a Y-axis which denotes the total drain-to-source resistance.
Many types of resistance-based method have been hithertofore proposed, among which the Terada-Muta-Chern method (referred to hereinafter as the TMC method) and the Shift and Ratio method (referred to hereinafter as the S&R method) are generally used.
First, the TMC method is described with reference to
FIGS. 26 and 27
. Expression (1) providing the relationship between the total drain-to-source resistance R
tot
, the effective channel length L
eff
, the resistance f per channel unit length and the series resistance R
sd
is transformed into Expression (4) by using Expression (2) providing the relationship between the effective channel length L
eff
, the mask channel length L
m
and the channel length reduction DL and Expression (3) providing a variable A.
R
tot
=L
eff
·f+R
sd
(1)
L
eff
=L
m
−DL (2)
A≡−DL·f+R
sd
(3)
R
tot
=L
m
·f+A (4)
It is found from Expression (4) that the resistance f per unit length and the variable A are determined from the relationship between the total drain-to-source resistance R
tot
and the mask channel length L
m
. The total drain-to-source resistance R
tot
, the mask channel length L
m
and the resistance f per unit length which serve as a function of the gate overdrive V
gt
must be determined, with the gate overdrive V
gt
held constant. As shown in
FIG. 26
, for example, a plurality of lines may be plotted for different gate overdrives V
gt1
, V
gt2
, . . . by measuring the total drain-to-source resistance R
tot
of MOS transistors having the mask channel length L
m
which takes values L
m1
to L
m4
. Then, values f
1
, f
2
, . . . of the resistance f per unit length and values A
1
, A
2
, . . . of the variable A defined in Expression (3) are found from the slopes and R
tot
-intercepts of the respective plotted lines.
With attention focused on Expression (3), the TMC method extracts the channel length reduction DL and the series resistance R
sd
based on the slope and R
tot
-intercept of the line of the graph of
FIG. 27
since the values f
1
, f
2
, . . . of the resistance f and the values A
1
, A
2
, . . . of the variable A which are found in the above described manner are in the relationship shown in the graph of FIG.
27
. The threshold voltage V
th
of the MOS transistor which serves as a reference for the calculation of the gate overdrive V
gt
is determined by extrapolation from a source-drain current versus gate voltage characteristic as shown in FIG.
28
.
The TMC method is of low extraction accuracy because of the uncertainty of the threshold voltage V
th
obtained by the extrapolation, and thus is not adaptable for an application to transistors which are not greater than 0.35 &mgr;m in channel length.
FIG. 29
shows the influence of the uncertainty of the gate overdrive V
gt
in the case where the mask channel length L
m
coordinate value DL* of the point of intersection is determined using two transistors. There is no problem if the gate overdrives V
gt
of the two transistors differ by the same amount from the true V
gt
. On the other hand, a 0.01 V difference in gate overdrive V
gt
between the two transistors, for example, causes an error on the order of slightly less than 0.01 &mgr;m. The extraction error of the threshold voltage V
th
of one of the transistors which has a shorter gate length due to the series resistance R
sd
is about −0.02 V when the extrapolation is used for the extraction of the threshold voltage V
th
. Thus, the extraction error of the channel length reduction DL resulting from the uncertainty of the threshold voltage V
th
is estimated to be about −0.01 to about −0.02 &mgr;m. Additionally, when data obtained by measuring the gate voltage V
gs
at intervals of 0.1 V are used, there is a likelihood that a quantization error causes the extraction error of the threshold voltage V
th
on the order of ±0.01V, thereby causing the extraction error of the channel length reduction DL.
Next, the S&R method is described below with reference to
FIGS. 30 and 31
. The S&R method provides the channel length reduction DL using Expression (5) using two MOS transistors Sh and Lo which are equal in mask channel width W
m
but differ in mask channel length L
m
. The MOS transistor Lo is a transistor having a channel length long enough to ignore the influence of the channel length reduction DL, and the MOS transistor Sh is a transistor having a shorter channel length.
DL
=
L
mSh
-
L
mLo
⟨
ri
⟩
(
5
)
where
ri
=
R
totLo
′
(
V
gs
)
R
totSh
′
(
V
gs
+
δ
0
)
where the marks “<>” denote an average value in a given region of the gate overdrive V
gt
, the prime denotes a first derivative with respect to the gate overdrive V
gt
, and &dgr;
0
is the difference (V
thSh
−V
thLo
) between the threshold voltages V
thSh
and V
thLo
of the two MOS transistors Sh and Lo.
In other words, the S&R method results in the problem of determining <ri> for the correct gate overdrive V
gt
. An algorithm for determining <ri> is as follows:
Step 1: extracting the threshold voltage V
thLo
of the transistor Lo
Step 2: shifting R
totSh
′to R
totSh
′+&dgr; to calculate the average value <ri> and a standard deviation &sgr; (ri) in a given region of the gate overdrive V
gtLo
(=V
gs
−V
thLo
) (See
FIG. 30
) Step 3: repeating Step 2, with the shift amount &dgr; changed Step 4: providing <ri> as <ri>&dgr;=&dgr;
0
where &dgr;
0
is the
Amishiro Hiroyuki
Maruyama Yuko
Yamaguchi Kenji
Nguyen Trung Q.
Nguyen Vinh P.
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