Device for ESD protection of an integrated circuit

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

Reexamination Certificate

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Details

C361S111000, C361S118000

Reexamination Certificate

active

11141986

ABSTRACT:
A device for ESD (electrostatic discharge) protection of a circuit of a semiconductor device comprises a field effect transistor based varistor with gate, source and drain regions, wherein one of the source and drain regions is connected to an input/output pad of the semiconductor device, and the other one of the source and drain regions is connected to an input/output terminal of the circuit. A biasing circuit is connected to the gate region of the varistor to create an accumulation region below the gate of the varistor at normal operating voltages of said semiconductor device. The semiconductor device is preferably an integrated device on a single substrate.

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