Device for ESD protection of an integrated circuit

Details Device for ESD protection of an integrated circuit Device for ESD protection of an integrated circuit

2007-01-16

2007-01-16

Sircus, Brian (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000

Reexamination Certificate

active

10874125

ABSTRACT:
A device for ESD protection of a high frequency circuit (1) of a semiconductor device comprises first (3) and second (4) p-type and first (6) and second (5) n-type JFET's, wherein the first p-type JFET (3) is connected with its gate to a high voltage source, its source to an input/output pad (2) of the semiconductor device, and its drain to the source of the first n-type JFET (6), the second p-type JFET (4) is connected with its gate to the high voltage source, its source to the drain of the second n-type JFET (5), and its drain to an input/output terminal of the circuit (1), the first n-type JFET transistor (6) is connected with its gate to ground (GND), and its drain to the input/output terminal, and the second n-type JFET transistor (5) is connected with its gate to ground (GND), and its source to the input/output pad (2).

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