Coded data generation or conversion – Digital code to digital code converters – To or from run length limited codes
Reexamination Certificate
2000-10-27
2001-08-14
JeanPierre, Pegut (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from run length limited codes
C341S050000
Reexamination Certificate
active
06275175
ABSTRACT:
The invention relates to a device for encoding a stream of databits of a binary source signal into a stream of databits of a binary channel signal, wherein the bitstream of the source signal is divided into n-bit source words, which device comprises converting means adapted to convert said source words into corresponding m-bit channel words, the converting means being adapted to convert a block of p consecutive n-bit source words into a corresponding block of p consecutive m-bit channel words, such that the conversion for each block of p consecutive n-bit source words is substantially parity preserving, where n, m and p are integers, m>n≧1, p>1, and where p can vary. The invention also relates to a recording device comprising the encoding device, for recording the channel signal on a record carrier, to the record carrier itself, to an encoding method, and to a device for decoding a stream of data bits of a binary channel signal obtained by means of the encoding device, so as to obtain a stream of databits of a binary source signal.
An encoding device mentioned in the foregoing is known from U.S. Pat. No. 5,477,222 (PHN 14448). The document discloses a device for encoding a stream of databits of a binary source signal into a stream of databits of a binary channel signal, satisfying a (
1
,
8
) runlength constraint. That means that, in a serial datastream of the channel signal at minimum one ‘zero’ and at maximum eight ‘zeroes’ are present between two consecutive ‘ones’ in the channel signal. It should be noted in this respect that normally an additional precoding step, such as a
1
T preceding, is applied to the (
1
,
8
) constrained sequence, resulting in a runlength limited sequence with minimum runlength
2
and maximum runlength
9
.
The known conversion is parity preserving. ‘Parity preserving’ means that the parity of the n-bit source words to be converted equal the parity (after modulo-2 addition) of the corresponding m-bit channel words in which they are converted. As a result, the n-to-m conversion device as claimed does not influence the polarity of the signal.
As the conversion is parity preserving, an efficient DC control can be applied, such as by inserting DC control bits in the datastream of the source words.
The invention has for its object to provide an improved device for encoding n-bit source words into corresponding m-bit channel words.
The device in accordance with the invention is characterized in that the converting means is adapted to convert the 8-bit bit sequence ‘00010001’ in the bitstream of the binary source signal into the 12-bit bit sequence ‘100010010010’ of the binary channel signal.
The device in accordance with the invention is also characterized by one of the claims
2
,
5
,
6
,
7
or
8
.
The invention is based on the recognition that, encoding in accordance with the known encoding device relatively long sequences comprising only the minimum transition runlength may occur, leading to a deterioration of the bit detection in a bitdetector in a receiver, following transmission and subsequent decoding of the channel signal in the receiver. In a channel signal satisfying a specific runlength constraint, such as (
1
,
7
) or (
1
,
8
), this means that relatively long sequences ‘. . . 0101010101 . . . ’ occur, resulting in relatively long sequences ‘. . . 001100110011 . . . ’ in the sequence after
1
T precoding.
The devices in accordance with the invention restrict the lengths of those sequences, so that an improved bitdetection in a receiver can be realized.
The encoding device in accordance with the invention can be used in combination with a bit-adder unit in which one bit is added to codewords of a certain length of the source signal. The signal obtained can be applied to the encoding device of the present invention. The channel signal of the encoding device is applied to a
1
T-precoder. The purpose of the bit-adder unit is to add a ‘0’- or a ‘1’-bit to the consecutive code words included in the input signal of the converter, so as to obtain a precoder output signal which is DC free, or includes a tracking pilot signal having a certain frequency. The precoder output signal is recorded on a record carrier. The adding of a ‘0’-bit in the input signal of the converter results in the polarity of the output signal of the
1
T precoder remaining the same. The adding of a ‘1’-bit results in a polarity inversion in the output signal of the
1
T precoder. The converter therefore influences the output signal of the
1
T precoder such that the running digital sum value of the output signal of the
1
T precoder can be controlled so as to have a desired pattern as a function of time.
REFERENCES:
patent: 5477222 (1995-12-01), Kahlman et al.
patent: 5552940 (1996-09-01), Umemoto et al.
patent: 5861825 (1999-01-01), Ino
patent: 6175318 (2001-01-01), Kahlman et al.
L.J. Greenstein, “Spectrum of a Binary Signal Block Coded for DC Suppression”, The Bell System Technical Journal, Jul.-Aug. 1974, pp. 1103-1106.
Kahlman Josephus A. H. M.
Nakagawa Toshiyuki
Nakamura Kousuke
Narahara Tatsuya
Shimpuku Yoshihide
Belk Michael E.
JeanPierre Pegut
U.S. Philips Corporation
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