Coded data generation or conversion – Digital code to digital code converters – To or from minimum d.c. level codes
Reexamination Certificate
1999-09-09
2001-07-24
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from minimum d.c. level codes
C340S398100, C360S040000, C375S237000, C375S238000, C375S239000
Reexamination Certificate
active
06265994
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a device for encoding a stream of databits of a binary source signal into a stream of databits of a binary channel signal, the device comprising
input means for receiving the binary source signal,
merging means for merging a q-bit merging word at equidistant positions in the binary source signal in response to a control signal, so as to obtain a composite binary source signal,
converting means for converting the composite binary source signal into said binary channel signal,
control signal generator means for generating said control signal,
output means for supplying said binary channel signal. The invention also relates to a device for decoding a stream of data bits of a binary channel signal obtained by means of the encoding device, so as to obtain a stream of databits of a binary source signal, to a recording device comprising the encoding device, to a record carrier obtained with the recording device and to a method of encoding the source signal.
An encoding device mentioned in the foregoing is known U.S. Pat. No. 5,477,222 (PHN 14448). The document discloses a device for encoding a stream of databits of a binary source signal into a stream of databits of a binary channel signal, satsifying a (1,8) runlength constraint. That means that, in a serial datastream of the channel signal at mimimum one ‘zero’ and at maximum eight ‘zeroes’ are present between two consecutive ‘ones’ in the channel signal. It should be noted in this respect that normally an additional precoding step, such as a 1T precoding, is applied to the (1,8) constrained sequence, resulting in a runlength limited sequence with minimum runlength 2 and maximum runlength 9.
The known conversion is parity preserving. ‘Parity preserving’ means that the parity of the n-bit source words to be converted equal the parity (after modulo-2 addition) of the corresponding m-bit channel words in which they are converted. As a result, the n-to-m conversion device as claimed does not influence the polarity of the signal.
As the conversion is parity preserving, an efficient DC control can be applied, such as by inserting DC control bits in the datastream of the source words.
SUMMARY OF THE INVENTION
The invention has for its object to provide an improved device for encoding n-bit source words into corresponding m-bit channel words.
The device in accordance with the invention comprises . . . copy claim
1
in its entirely]. The invention is based on the following recognition. Without applying the measure in accordance with the invention, the encoding process is as follows. After insertion of the q-bit merging words in the bitstream of the binary source signal, a bitstream of the composite binary source signal has been generated. This composite binary source signal is divided into a sequence of subsequent n-bit words for conversion into m-bit channel words in the converting means. This division into a sequence of n-bit words is done such that one boundary between two subsequent words in the composite binary source signal may lie between a merging word and the subsequent source word of the binary source signal in said composite binary source signal. Until the next merging word, all boundaries between two subsequent words in the composite binary source signal are aligned with the boundaries between the subsequent source words of the binary source signal. The said next merging word forms, together with the first q bits of the next source word in the binary source signal, the next n-bit word in the composite binary source signal. As a result, until the following merging word, all boundaries between two subsequent words in the composite source signal are not aligned anymore with the boundaries of the n-bit source words of the binary source signal. Or, an n-bit word in the composite binary source signal is spread out across two subsequent n-bit source words of the binary source signal.
The n-bit words in the composite binary source signal are converted upon encoding into corresponding m-bit channel words. After transmission and subsequent reception in a receiver provided with a corresponding decoder, the m-bit channel words are decoded into corresponding n-bit words, which n-bit words form a replica of the composite binary source signal. Subsequently, the q-bit merging words are deleted from the composite binary source signal so as to obtain a replica of the binary source signal.
Errors may occur during transmission, resulting in an erroneous decoding in the decoder. An erroneous word in the replica of the composite binary source signal may lead to one erroneous source word in the replica of the binary source signal, namely for those portions of the replica of the binary source signal where the boundaries between two subsequent source words were aligned with the boundaries of two subsequent words of the replica of the composite binary source signal. However, in those portions of the replica of the binary source signal where the boundaries between two subsequent source words are not aligned with the boundaries of two subsequent words of the replica of the composite binary source signal, an erroneous word in the replica of the composite source signal leads to two erroneous words in the replica of the binary source signal.
The invention overcomes this error propagation, in that by shifting q bits in each second group of y consecutive bits source words in the binary source signal, the boundaries between two subsequent n-bit source words of the binary source signal are aligned with the boundaries between two subsequent n-bit words in the composite binary source signal. As a result, no error propagation will occur.
Generally, the channel signal obtained is applied to a 1T-precoder. The purpose of the merging means is to add merging words, such as a 1-bit merging word, that is: a ‘0’- or a ‘1’ bit, to the consecutive code words included in the input signal of the converting means, so as to obtain a precoder output signal which is DC free, or includes a tracking pilot signal having a certain frequency. The precoder output signal is recorded on a record carrier.
In the example of q=1, the adding of a ‘0’-bit in the input signal of the converter results in the polarity of the output signal of the 1T precoder remaining the same. The adding of a ‘1’-bit results in a polarity inversion in the output signal of the 1T precoder. The merging means therefore influences the output signal of the 1T precoder such that the running digital sum value of the output signal of the 1T precoder can be controlled so as to have a desired pattern as a function of time.
REFERENCES:
patent: 4536472 (1985-08-01), Immink
patent: 4573034 (1986-02-01), Immink
patent: 5477222 (1995-12-01), Kahlman et al.
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patent: 6061005 (2000-05-01), Van Rooyen et al.
patent: 6157327 (2000-12-01), Akaogi
patent: 6175318 (2001-01-01), Kahlman et al.
Belk Michael E.
Mai Lam T.
Tokar Michael
U.S. Philips Corporation
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