Coded data generation or conversion – Digital code to digital code converters – To or from minimum d.c. level codes
Reexamination Certificate
1998-10-23
2001-05-01
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from minimum d.c. level codes
C341S059000
Reexamination Certificate
active
06225921
ABSTRACT:
The invention relates to a device for encoding a stream of databits of a binary source signal into a stream of databits of a binary channel signal satisfying a predetermined (d,k) constraint, wherein the bitstream of the source signal is divided into n-bit source words, which device comprises converting means adapted to convert said source words into corresponding m-bit channel words, the converting means being adapted to convert a block of p consecutive n-bit source words into a corresponding block of p consecutive m-bit channel words, such that the conversion for each block of p consecutive n-bit source words is substantially parity preserving, where n, m and p are integers, m>n≧1, p≧1, and where p can vary. The invention also relates to a recording device comprising the encoding device for recording the channel signal on a record carrier, to the record carrier itself, to an encoding method, and to a device for decoding a stream of data bits of a binary channel signal obtained by means of the encoding device, so as to obtain a stream of data bits of a binary source signal.
An encoding device mentioned in the foregoing is known from U.S. Pat. No. 5,477,222 (PHN 14448). The document discloses a device for encoding a stream of data bits of a binary source signal into a stream of data bits of a binary channel signal satisfying a (1,8) runlength constraint. That means that, in the serial datastream of the channel signal at minimum one ‘zero’ and at maximum eight ‘zeroes’ are present between two consecutive ‘ones’ in the channel signal. It should be noted in this respect that normally an additional precoding, such as a well known 1T precoding is applied to the (1,8) d,k constrained sequence, resulting in a runlength limited sequence with minimum runlength 2 and maximum runlength 9.
The known conversion is parity preserving. ‘Parity preserving’ means that the parity of the n-bit source words to be converted equal the parity (after modulo-2 addition) of the corresponding m-bit channel words in which they are converted. As a result, the n-to-m conversion device as claimed does not influence the polarity of the signal.
As the conversion is parity preserving, an efficient DC control can be applied, such as by inserting Dc control bits in the datastream of the source words.
The invention has for its object to provide for an appropriate sync word to be inserted into the serial datastream of the channel signal.
The device in accordance with the invention is characterized in that the device comprises sync word generator means for generating a q-bit sync word also satisfying said (d,k) constraint, the said sync word starting with a ‘0’ bit and ending with a ‘0’ bit, the device further comprising merging means for merging said sync word in said stream of databits of the binary channel signal, and that q is an integer value larger than k.
It is well known in the art to add sync words to a serial datastream of a channel signal. Reference is made in this respect to WO 96/31,880. The sync word proposed violates the prescribed k constraint. This has its disadvantages in that a relatively long sync word is required, that is more prone to error and results in a relatively large overhead.
In accordance with the invention, a q-bit sync word is proposed, such that, after combining the sequence of channel words with the sync word, the signal obtained satisfies said (d,k) constraint. This has the advantage that a shorter sync word is required, resulting in a smaller overhead. Further, as the said sync word starts with a ‘0’ bit and ends with a ‘0’ bit, it can be merged between any m-bit channel word, eg. when taking d equal to 1.
Preferably, the sync word starts with a ‘01’ bitsequence and ends with a ‘10’ sequence. This provides for satisfying the k constraint.
In an embodiment, in which the encoding device generates a channel signal satisfying the constraint d=1, preferably a 15-bit sync word is used, such as the sync word ‘010000000010010’. When k=8, this sync word satisfies the formula q=2k−1, and is very efficient, even when compared with eg other sync words that do not violate the d,k constraints of the signals they are merged in, such as disclosed in U.S. Pat. No. 4,501,000 (PHQ 80.007). It should however be noted that the sync word defined above could be equally well used in an encoding device supplying an output datastream satisfying another k-constraint, such as k=7 or lower (so that the sync word does not satisfy the k constraint of the encoded signal), or k larger than 8.
In another embodiment, a sync word is generated starting with a ‘01’ bitsequence and ending with a ‘100’ bitsequence, such as the 16-bit sync word ‘0100000000100100’.
In again another embodiment, a sync word is generated starting with a ‘01’ bitsequence and ending with a ‘1000’ bitsequence, such as the 17-bit sync word ‘01000000001001000’.
In a further embodiment, a sync word is generated starting with a ‘01’ bitsequence and ending with a ‘10000’ bitsequence, such as the 18-bit sync word ‘010000000010010000’.
For certain n-to-m conversions, the sync words ending with two or more ‘zeroes’ may lead, after concatenation with a subsequent channel word and with an unmodified encoding, to a violation of the k-constraint. This can be overcome by changing the conversion, so that the k-constraint is satisfied, with a local violation of the parity preserving property.
The encoding device in accordance with the invention can be used in combination with a bit-adder unit in which one bit is added to codewords of a certain length of the source signal. The signal obtained can be applied to the encoding device of the present invention. The channel signal of the encoding device is applied to a 1T-precoder. The purpose of the bit-adder unit is to add a ‘0’- or a ‘1’-bit to the consecutive code words included in the input signal of the converter, so as to obtain a precoder output signal which is DC free, or includes a tracking pilot signal having a certain frequency. The precoder output signal is recorded on a record carrier. The adding of a ‘0’-bit in the input signal of the converter results in the polarity of the output signal of the 1T precoder remaining the same. The adding of a ‘1’-bit results in a polarity inversion in the output signal of the 1T precoder. The converter therefore influences the output signal of the 1T precoder such that the running digital sum value of the output signal of the 1T precoder can be controlled so as to have a desired pattern as a function of time.
REFERENCES:
patent: 4641128 (1987-02-01), Schouhamer Immink
patent: 4728929 (1988-03-01), Tanaka
patent: 5142421 (1992-08-01), Kahlman et al.
patent: 5477222 (1995-12-01), Kahlman et al.
Kahlman Josephus A. H. M.
Nakagawa Toshiyuki
Nakamura Kousuke
Narahara Tatsuya
Schouhamer Immink Kornelis A.
Belk Michael E
U.S. Philips Corporation
Wamsley Patrick
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