Coded data generation or conversion – Digital code to digital code converters – To or from run length limited codes
Reexamination Certificate
2001-05-30
2003-04-08
Young, Brian (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from run length limited codes
Reexamination Certificate
active
06545615
ABSTRACT:
The present invention relates to a device for encoding a stream of databits of a binary source signal into a stream of databits of a binary channel signal, wherein the bitstream of the source signal is divided into n-bit source words, which device comprises converting means adapted to convert a block of p consecutive n-bit source words into a corresponding block of p consecutive m-bit channel words, where p, n, m are integers and m>n≧1, the converting means comprising memory means which contain for each n-bit source word a number of m-bit channel words, arranged in coding states, and a corresponding state number, indicating the memory location for a next m-bit channel word.
Such a device is known from WO97/09718/A1 and describes a recording and reproducing system, provided with a memory, which, in response to n-bit source words and respective table numbers, generates m-bit channel words and state numbers for next source word conversions. The conversions are not parity preserving. Further said known device comprises a selection circuit, which, in response to the m-bit channel words, calculates the running DSV (digital sum value) and provides for selection signals which indicate whether the read out channel words have to increase or decrease the DSV. Although by these measures the dc-level may be incidentally reduced, an overall dc-suppression is not guaranteed, with the consequence that still distortions may be introduced in communicating systems which cannot handle a dc-component, as well as distortions in any recording of data on respective carriers.
In order to obtain a required dc-suppression, dc-control bits can be introduced on source level, however, with the consequence that the channel words do not correspond with the source words any longer. This means that, when there is an error on a data carrier, error propagation during reproducing may occur.
Further, in practice several encoding systems are known, e.g. in CD-recording and reproducing systems EFM-encoding of 8-bit source words into 17-bit channel words is applied. During recording the encoded channel words are recorded on a data carrier, while during reproducing the channel words are decoded inversely. In DVD-recording and reproducing systems EFM-plus-encoding of 8-bit source words into 16-bit channel words is applied. The channel signals therein are realized in a (2,10) sequence. However, in all these known systems a dc-suppression in the channel word sequence is not guaranteed.
Referring to the above it may be noticed that encoding devices in general provide for encoded channel words in a (d,k) sequence, wherein d is the number of ‘zeros’ which at least is present between two subsequent ‘ones’ in the serial datastream of the channel signal and k the number of ‘zeros’ which at most is present between two subsequent ‘ones’ in the serial datastream of the channel signal. The description in said international patent application shows a conversion of blocks of 8-bit source words into blocks of 15-bit channel words in a (2,14) sequence. Although, by the presence in the memory of several coding tables, the sequence of channel words obeys the d,k-constraints, a dc-suppression, as already mentioned, is not guaranteed, because the separate conversions of n-bit source words into m-bit channel words are not parity preserving.
The purpose of the invention is to obtain an encoding device as described in the opening paragraph in which a dc-suppression in the channel word sequence is guaranteed and in which, when there is an error on a data carrier, error propagation during reproducing is avoided.
Therefore, in a first embodiment according to the invention, the device as described in the opening paragraph is characterized in that the conversion for at least most of the n-bit source words is parity preserving and/or parity inverting and that after each block of source words q dc-control sourcebits are added, which dc-control sourcebits are converted into r dc-control channelbits. In a second embodiment according to the invention, the device is characterized in that the conversion for at least most of the n-bit source words is parity preserving and/or parity inverting an that after each block of source words q dc-control sourcebits are added, which dc-control sourcebits together with only a following n-bit source word is converted into a (r+m)-bit channelword, where q and r are integers. In both cases all the source words correspond with respective channel words; in other words, source words and channel words are permanently aligned with each other. By this measure error propagation will be avoided. As in the second embodiment a separate table is provided for the conversion of (n+q)-bit source words into (m+r)-bit channel words, which is more complicated than a simple table for the conversion of q-bit dc-control source bits into r dc-control channel bits, the first embodiment is preferred.
Although parity preserving codes are known per se, instead of a parity preserving conversion of source words into channel words, also a parity inverting conversion may be applied. The conversion is parity preserving when, if the number of ‘ones’ in a source word is even, the number of ‘ones’ in a corresponding channel word is even too, and, if the number of ‘ones’ in a source word is odd, the number of ‘ones’ in a corresponding channel words is odd too. The conversion is parity inverting when, if the number of ‘ones’ in a source word is even, the number of ‘ones’ in a corresponding channel word is odd, and, if the number of ‘ones’ in a source words is odd, the number of ‘ones in a corresponding channel words is even. In both cases the insertion of a dc-control bit provides for parity conversion
In both embodiments the channel output signal sequence supplied by the converting means may be fed to a precoder to determine a RLL (run length limited) output signal, which signal is supplied to a control signal generator to derive the dc-control bits. Such a feedback loop for a parity preserving code is described in e.g. U.S. Pat. No. 5,477,222, wherein between successive groups of p consecutive n-bit source words parity preserving bits are inserted in such a way that channel words obtained thereafter do not correspond with source words any longer and propagation errors may occur.
Like source word-to-channel word conversions, the dc-control source bits-to-dc-control channel bits conversion will depend on the last m-bit channel word, determining the state of the dc-control channel bits. Therefore, according to the invention the memory means further contain for each q dc-control source bits and for each state number r dc-control channel bits and a corresponding state number, indicating the memory location for a next m-bit channel word.
In a practical embodiment n=8, m=15, q=1 and r=2, while p may be chosen dependent on the desired dc-suppression. With a conversion rate 8/15 each source byte will correspond to a 15-bit channelword in one of the tables in the memory means, independently of the dc-control bits inserted.
When in a (d,k) channel word sequence in said practical embodiment d=2 and, for example a source code in the preferred embodiment ends with “1”, the dc-control bits will always be “00” as the next channel word may start with “1” and at least two zero's must be present between two “1's”. This means that the control bits itself have no influence with respect to parity control. Therefore, in order to realize a parity control in this case and in suchlike cases, according to the invention, the device comprises inverting means, which, depending on a last preceding channelword and on the dc-control channelbits, provides for inversion of an odd number of bits of a following source word; i.e. the inversion of 1, 3, 5, bits of a following source word. Such an inversion identifies dc-control source bit-to-dc control channel bit conversions with dc-control channel bits of the same parity, when the following channel word is chosen from another coding state belonging to a respective source
Kahlman Josephus Arnoldus Henricus Maria
Schouhamer Immink Kornelis Antonie
Belk Michael E.
Koninklijke Philips Electronics , N.V.
Young Brian
LandOfFree
DEVICE FOR ENCODING A STREAM OF DATABITS OF A BINARY SOURCE... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with DEVICE FOR ENCODING A STREAM OF DATABITS OF A BINARY SOURCE..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DEVICE FOR ENCODING A STREAM OF DATABITS OF A BINARY SOURCE... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3014345