Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2002-07-29
2004-03-09
Nguyen, Minh (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S159000, C331S00100A, C375S376000
Reexamination Certificate
active
06703875
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of synchronizing signals. Specifically, embodiments of the present invention relate to a device and method for emulating a phase-locked loop.
BACKGROUND ART
There are many applications in which it is desirable to create one or more signals that are phase-locked to a reference signal that is at a different frequency from the signal or signals. For example, a device in a network may synchronize an internal clock to a network clock in order to allow internal components that run at different frequencies than the network clock to be able to communicate on the network.
Standards for the accuracy of the internal clock, as well as the degree to which it is synchronized to the reference network clock, have been defined by the American National Standards Institute (ANSI). For example, ANSI has defined performance requirements regarding clocks in digital networks in the document entitled, “Synchronization Interface Standards for Digital Networks,” ANSI/T1.101-1998. In particular, that standard defines four stratum levels (and additional substrata). Stratum 1 has the most stringent requirements and the clock may be a completely autonomous source of timing. On the other hand, stratum-2, stratum-3, and stratum-4 may track an input clock at the same or a higher stratum level. Stratum-4 has the least stringent timing requirements.
One type of device within a network that may need to synchronize to a network reference clock is customer premises equipment (CPE). For example, CPEs often derive a reference clock from the network to drive their backplane TDM (Time Division Multiplexing) bus and may also pass one or more clocks downstream to other devices. Being at the lower end of the network, CPEs generally are not subject to the most stringent clock standards and as such, may only need to meet the requirements of stratum-4 or stratum-4E. Thus, CPEs may synchronize to a network clock that is a stratum-4 clock or higher.
Conventionally, a phase-locked loop may be used to frequency and phase-lock to a clock such as a network clock, while meeting stratum-4 or stratum-4E requirements for the internal synchronized clock. The phase-locked loop may generate multiple clocks that are at frequencies other than the network clock, but phase-locked to it. However, conventional phase-locked loops have several drawbacks.
One problem with conventional digital phase-locked loops is that they are generally designed to lock to a specific reference frequency. For example, the digital phase-locked loop may have a reference oscillator that is either some integral multiple or very close to an integral multiple of the desired frequency. The reference frequency to which it locks must be at or very near the frequency of the reference oscillator. Frequently, this is on the order of Megahertz. If the reference frequency is not near the frequency for which the phase-locked loop was designed, then it will not function and a different phase-locked loop will be required. Sometimes, a custom phase-locked loop that is able to synchronize to the desired frequency must be built.
A further drawback with conventional phase-locked loops is that they add considerable cost to the system. For example, analog phase-locked loops require external components such as resistors and capacitors to implement loop filters to tune to the desired frequency, thus adding considerable expense.
Additionally, the external components may be temperature sensitive and hence the designer must factor in possible temperature variations. If the designer fails to properly do so, the phase-locked loop may fail to accurately synchronize to the reference.
Therefore, it would be advantageous to provide a method and device for providing a phase-locked loop to synchronize an output signal to a reference signal. It would be further advantageous if the method and device is able to phase-lock to a network reference clock. It would be further advantageous that the output signal is a clock that is ANSI stratum-4 compliant. It would be still further advantageous that the above method and device is cost efficient. It would be even further advantageous if the method and device is not highly sensitive to temperature variations.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide a method and device for emulating a phase-locked loop that may synchronize an output signal to a reference signal. Embodiments of the present invention phase-lock to a network reference clock. Embodiments of the present invention provide a clock signal that is ANSI stratum-4 compliant. Embodiments of the present invention are cost efficient. Embodiments of the present invention are not highly sensitive to temperature variations.
A device for emulating a phase-locked loop is disclosed. The device comprises a correction table for storing a digital pattern describing how a frequency of a signal is to be altered. The device also has first logic for receiving a sample signal and altering its frequency based on the correction table output to produce a desired output signal that is near a desired frequency. The first logic accomplishes this by dividing the frequency of the sample signal by a first or a second integer based on the correction table output. Further, the device has second logic for adjusting the frequency of the output signal to the approximate frequency of a reference signal. Additionally, the device has comparison logic for comparing the reference signal with the adjusted output signal and modifying the output of the correction table to substantially phase-lock the output signal to the reference signal.
Another embodiment provides for a method of emulating a phase-locked loop. The method comprises receiving a base signal and a frequency modification signal into logic for altering a frequency of a signal. To produce an output signal, the frequency of the base signal is divided by a first integer if the frequency modification signal is a first value and divided by a second integer if the frequency modification signal is a second value. The frequency of the output signal is altered to substantially match a frequency of a reference signal. The altered output signal fed back and compared to the reference signal. Then, the frequency modification signal is modified in response to the comparison to substantially phase lock the output signal to the reference signal.
These and other advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
REFERENCES:
patent: 5295079 (1994-03-01), Wong et al.
patent: 6078633 (2000-06-01), Shiotsu et al.
patent: 6366174 (2002-04-01), Berry et al.
patent: 6404249 (2002-06-01), Hayashida
Cisco Technology Inc.
Nguyen Minh
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