Device for electrostatic discharge protection

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With pn junction isolation

Reexamination Certificate

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Details

C257S373000, C257S355000

Reexamination Certificate

active

07030461

ABSTRACT:
The present invention is related to an Electrostatic Discharge protection device. This may be a semiconductor device such as a CMOS transistor, having a snap-back IV characteristic, in order to withstand ESD pulses. The device of the invention comprises an additional doped region, which influences the internal resistance of the substrate whereupon the device is built. This has a positive effect on the snap-back characteristic, putting the snap back trigger voltage and current at a lower value, compared to prior art devices.

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Duvvury, et al., “Substrate Pump NMOS for ESD Protection Applications”, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000, Sep. 26-28, 11 pgs.
Y. Blecher and R. Fried, “Zener Substrate Triggering for CMOS ESD Protection Devices”, Electronics Letters, IEE Stevenage, Great Britain, Oct. 24, 1996, vol. 32, No. 22, 2 pgs.
A. Amerasekera, et al., “Substrate Triggering and Salicide Effects on ESD Performance and Protection Circuit Design in Deep Submicron CMOS Processes”, Electron Devices Meeting, 1995, IEEE, Dec. 10, 1995, 4 pgs.

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