Static information storage and retrieval – Floating gate – Particular biasing
Patent
1993-06-11
1995-11-21
Popek, Joseph A.
Static information storage and retrieval
Floating gate
Particular biasing
365207, 365208, 327 51, G11C 700
Patent
active
054693829
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a device for detecting the contents of the cells contained in a memory, especially an EPROM memory. It also concerns a method implemented with this device, as well as a memory provided with this device.
2. Discussion of Background Art
Present progress in memories of very high capacities, especially of EPROM type, has been accompanied by an increase in the working frequencies of the systems in which these memories are implemented, and consequently by the search for ever shorter times for access to the contents of the cells constituting these memories. Now, in order to minimize the access time of a memory, especially a memory of EPROM type, it is essential to preset the detection amplifier normally allowed for in order to permit the reading of the contents of each cell in a state in which the differential inputs are balanced.
Hitherto, in the earlier designs of this detection amplifier, this presetting was performed using a pulse to short-circuit the differential inputs directly. However, this has the disadvantage of generating spurious current spikes both in the reference column and in the bit row, this having the consequence of disturbing the state of the current comparator and consequently of leading to an increase in the access time.
SUMMARY OF THE INVENTION
The aim of the invention is to remedy these disadvantages by providing a device for detecting the contents of the cells of a memory, especially an EPROM memory, these cells being organized as a set of bit lines, this device comprising means for comparing a reference current associated with a reference column and a read current invoked in a cell of a bit lines and whose contents are to be read, said comparison means comprising a resistive reference element and a resistive read element through which the reference and read currents respectively travel, and which are connected, on the one hand, to a supply voltage source and, on the other hand, to a non-inverting input and to an inverting input respectively of a differential amplifier delivering as output a detection cue.
According to the invention, the device furthermore comprises means for selectively connecting the output of the differential amplifier to its inverting input for a predetermined preloading period.
Thus, it is the differential stage itself which is used to balance the differential inputs, by passing from a differential mode to a follower mode for a predetermined period. This also has the effect of compensating for the asymmetries which general exist in the input transistors of the differential stage.
Furthermore, since the entire preloading current travels towards the bit line, the reference column is not disturbed by the preloading operation, this having the effect of improving the stability of the reference column during the detection operation.
According to an advantageous embodiment, the selective connecting means comprise switching means controlled by a cyclic preloading clock signal.
According to another aspect of the invention, the method of detecting the contents of cells of a memory, especially of EPROM type, implemented in the device according to the invention, comprising, for each read sequence for a cell, a step of preloading this device, followed by a step of reading the contents of said cell comprising a comparison of the read current flowing in said cell with a reference current, this comparison being made by a differential amplifier, is such that, during the preloading step, the differential amplifier is switched into follower mode during a preloading clock cycle.
According to yet another aspect of the invention, the erasable permanent memory, especially of EPROM type, incorporating devices according to the invention, is such that it comprises control means for generating, in the course of a preloading clock cycle, a signal for controlling the means for selectively connecting the output to the inverting input of the differential amplifier of each of the detection devices.
Other feat
REFERENCES:
patent: 4004157 (1977-01-01), Baertsch et al.
patent: 4068136 (1978-01-01), Minami
patent: 4151429 (1979-04-01), Hupe 307530
Patent Abstracts of Japan, vol. 4, No. 97, (E-18) Jul. 12, 1980 & JP-A-55061136 (Fujitsu) May 8, 1980.
Dinh Son
Popek Joseph A.
SGS-Thomson Microelectronics S.A.
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