Device for delaying clock signal

Details Device for delaying clock signal Device for delaying clock signal

1998-07-30

2000-05-09

Zweizig, Jeffrey

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327152, 327276, 327291, H03H 1126

Patent

active

060609281

ABSTRACT:
Device for delaying a clock signal using a ring delay is disclosed. The device can include a delay for delaying an external clock signal eCLK as much as time delays d1+d2 of a time delay d1 occurring on reception and a time delay d2 occurring on driving an output buffer, a pulse generator for receiving the clock signal from the delay and generating rectangular pulses synchronous to rising edges, and a ring delay having a plurality of unit delays connected in a ring form for delaying and circulating the pulse signal generated in the pulse generator as well as latching a signal from each unit delay synchronous to the clock signal rCLK received in the chip. The first clock signal delay is for delaying the clock signal rCLK in a course corresponding to a number of circulation, and a second clock signal delay is for making a fine delay of the clock signal from the first clock signal delay in response to a latch signal from the ring delay. A reset signal generator is for resetting the ring delay and the first, and second clock signal delays in response to the clock signal rCLK.

REFERENCES:
patent: 5526393 (1996-06-01), Konodo et al.
patent: 5534809 (1996-07-01), Watanabe et al.
Takanori Saeki et al.; "A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Display;" IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996; pp. 1656-1668.
Ian Young et al.; "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors;" IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992; pp. 1599-1607.
Thomas H. Lee et al.; "A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM;" IEEE Journal of Solid State Circuits, vol. 29, No. 12, Dec. 1994; pp. 1491-1496.

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