Device for controlling the switchover of processor operation fro

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Details

395800, 36492792, 36493362, 364DIG2, G06F 922

Patent

active

056714238

DESCRIPTION:

BRIEF SUMMARY
Programmable controllers are often used to solve automation tasks, these controllers solving the automation task based on a control program stored in a memory. The program is customarily structured in the memory such that the corresponding processor in the programmable controller can execute this program serially.
A programmable controller of this sort is known from the "Siemens-Programmierhandbuch fur Ablaufsteuerungen mit S5-110 A, SIMATIC S5-110 A, SIMATIC S5", 1983!. A control program designed for binary signal processing is created with a programming device in a programming language and stored in a memory. During the operation of the controller, the individual instructions of the control program are, corresponding to execution with a Von Neumann machine, read out from memory one by one, interpreted and the corresponding operations (e.g., logic operations on the process input and output data) executed. Due to the serial execution of the control program, the reaction time to status changes in the input data is dependent on the program length and the execution time of each instruction.
In order to reduce the reaction time, it is advantageous to equip a programmable controller with a device known from the DE-OS 37 43 438. With this device, a switchover to a subsequent status and a transfer of new stored in a status register for a current status and the input vector assignment of digital process input parameters. With this known device, a status switchover of only one processor can be controlled.
The underlying object of the present invention is to create a device of the type named in the introduction which allows a status switchover from an instantaneous status to a subsequent status for several processors.
This objective is solved by the measures specified in the characterizing part of claim 1.
In one refinement of the invention, the synchronization of the status switchovers of the different processor operating statuses is made possible by the fact that a status code is not loaded into one status register until a certain status code is stored in the other status register.
The device according to the invention is intended in particular for programmable controllers, referred to as programmable status controllers.
The invention is explained hereafter in greater detail based on an
The following are shown:
FIG. 1 a block diagram of a controlling system according to the invention, and
FIG. 2 a data set of selectable control data and subsequent status codes.
The controlling system according to FIG. 1 is used to control the switchover of processor operating statuses from an instantaneous status to a subsequent status. The instantaneous status with which the controlling system is put into operation can be any status of a processor. Thus, there is no loss of generality if the reset status is considered henceforth as the initial status of the controlling system.
On the signal path 1, the code Z0 of the instantaneous status is loaded from outside into the status register 2, or it is preset there on the basis of a reset signal. The control unit 3 receives the code Z0 from the status register 2 and causes via the signal path 5 to the page selector 6 in the data storage unit 7 the data storage area 7a (cf. FIG. 2) to control data S0, S1, S2 specific to the instantaneous status as well as codes Z0, Z1, Z2 for the subsequent statuses reachable from the instantaneous status.
The input stage 15 reports a change in at least one of the process input parameters E0 . . . which are taken into account, i.e., a switchover to a new input vector assignment, to the control unit 3 via the signal path 14 which control unit 3 causes in response via the signal path 10 the row selector 11 to select the subarea from the data storage area 7a activated in the data storage unit 7 which subarea contains the control data S0, S1 or S2 specific to the new input vector assignment and the code Z0, Z1 or Z2 of the subsequent status determined by the new input vector assignment.
In order to illustrate the selection of the data storage area 7a and th

REFERENCES:
patent: 4336588 (1982-06-01), Vernon et al.
patent: 5202998 (1993-04-01), Yanes
patent: 5230001 (1993-07-01), Chandra et al.
patent: 5321603 (1994-06-01), Schwenke
Siemens A.G., Simatic S5, Programmierhandbuch fur Ablaufsteuerungen mit S5-110A; Von Egon Edinger et al., 1983, 8 pages.

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